CY7B993V, CY7B994V

Document #: 38-07127 Rev. *J

Page 6 of 18

Block Diagram Description

Phase Frequency Detector and Filter

These two blocks accept signals from the REF inputs (REFA+,

REFA–, REFB+, or REFB–) and the FB inputs (FBKA+, FBKA–,

FBKB+, or FBKB–). Correction information is then generated to

control the frequency of the voltage-controlled oscillator (VCO).

These two blocks, along with the VCO, form a PLL that tracks

the incoming REF signal.

The CY7B993V/994V have a flexible REF and FB input scheme.

These inputs allow the use of either differential LVPECL or

single-ended LVTTL inputs. To configure as single-ended LVTTL

inputs, the complementary pin must be left open (internally pulled

to 1.5V). The other input pin can then be used as an LVTTL input.

The REF inputs are also tolerant to hot insertion.

The REF inputs can be changed dynamically. When changing

from one reference input to the other of the same frequency, the

PLL is optimized to ensure that the clock output period is not less

period deviation)) while reacquiring the lock.

VCO, Control Logic, Divider, and Phase Generator

The VCO accepts analog control inputs from the PLL filter block.

The FS control pin setting determines the nominal operational

from 12 MHz to 100 MHz, and a high-speed device (CY7B994V)

that ranges from 24 MHz to 200 MHz. The FS setting for each

device is shown in Table 2.

200 MHz.

FBDS[0:1]

Input

3-level

Input

Feedback Divider Function Select. These inputs determine the function of the QFA0

and QFA1 outputs (see Table 5).

FBDIS

Input

LVTTL

Feedback Disable. This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1]

is disabled to the “HOLD-OFF” or “High Z” state; the disable state is determined by

OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see Table 6). This input has an

internal pull-down.

[1:4]F[0:1]

Input

3-level

Input

Output Phase Function Select. Each pair controls the phase function of the respective

bank of outputs (see Table 4).

[1:4]DS[0:1]

Input

3-level

Input

Output Divider Function Select. Each pair controls the divider function of the respective

bank of outputs (see Table 5).

DIS[1:4]

Input

LVTTL

Output Disable. Each input controls the state of the respective output bank. When HIGH,

the output bank is disabled to the “HOLD-OFF” or “High Z” state; the disable state is

determined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see

Table 6). These inputs each have an internal pull-down.

INV3

Input

3-level

Input

Invert Mode. This input only affects Bank 3. When this input is LOW, each matched output

pair becomes complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is HIGH,

all four outputs in the same bank are inverted. When this input is MID all four outputs are

non inverting.

LOCK

Output LVTTL

PLL Lock Indicator. When HIGH, this output indicates the internal PLL is locked to the

reference signal. When LOW, the PLL is attempting to acquire lock.

OUTPUT_MODE Input

3-Level

Input

Output Mode. This pin determines the clock outputs’ disable state. When this input is

HIGH, the clock outputs disable to high impedance (High Z). When this input is LOW, the

clock outputs disable to “HOLD-OFF” mode. When in MID, the device enters factory test

mode.

QFA[0:1]

Output LVTTL

Clock Feedback Output. This pair of clock outputs is intended to be connected to the

FB input. These outputs have numerous divide options and three choices of phase adjust-

ments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.

[1:4]Q[A:B][0:1]

Output LVTTL

Clock Output. These outputs provide numerous divide and phase select functions deter-

mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.

VCCN

PWR

Output Buffer Power. Power supply for each output pair.

VCCQ

PWR

Internal Power. Power supply for the internal circuitry.

GND

PWR

Device Ground.

Pin Name

I/O

Pin Type

Pin Description

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