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CY7B994V-5BBCT Datasheet(PDF) 5 Page - Cypress Semiconductor |
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CY7B994V-5BBCT Datasheet(HTML) 5 Page - Cypress Semiconductor |
5 / 18 page RoboClock CY7B993V, CY7B994V Document #: 38-07127 Rev. *J Page 5 of 18 Figure 2. Pin Diagram – 100-Pin BGA Table 1. Pin Definition [1] Pin Name I/O Pin Type Pin Description FBSEL Input LVTTL Feedback Input Select. When LOW, FBKA inputs are selected. When HIGH, the FBKB inputs are selected. This input has an internal pull-down. FBKA+, FBKA– FBKB+, FBKB– Input LVTTL/ LVDIFF Feedback Inputs. One pair of inputs selected by the FBSEL is used to feedback the clock output xQn to the phase detector. The PLL operates such that the rising edges of the reference and feedback signals are aligned in both phase and frequency. These inputs can operate as differential PECL or single-ended TTL inputs. When operating as a single-ended LVTTL input, the complementary input must be left open. REFA+, REFA– REFB+, REFB– Input LVTTL/ LVDIFF Reference Inputs. These inputs can operate as differential PECL or single-ended TTL reference inputs to the PLL. When operating as a single-ended LVTTL input, the comple- mentary input must be left open. REFSEL Input LVTTL Reference Select Input. The REFSEL input controls how the reference input is configured. When LOW, it uses the REFA pair as the reference input. When HIGH, it uses the REFB pair as the reference input. This input has an internal pull-down. FS Input 3-level Input Frequency Select. This input must be set according to the nominal frequency (fNOM) (see Table 2). FBF0 Input 3-level Input Feedback Output Phase Function Select. This input determines the phase function of the Feedback bank’s QFA[0:1] outputs (see Table 4). Note 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. Pinouts (continued) 12 3456 789 10 A 1QB1 1QB0 1QA1 1QA0 QFA0 QFA1 FBKB+ VCCQ FBKA– FBKA+ B VCCN VCCN VCCN VCCN VCCN VCCN VCCQ FBKB– FBSEL REFA+ C GND GND GND GND GND GND VCCQ GND GND REFA– D LOCK 4F0 (3_level) 3F1 (3_level) GND FBDS1 (3_level) FBDS0 (3_level) 2F0 (3_level) VCCQ REFSEL REFB– E 4QB1 VCCN 4DS1 (3_level) GND 3F0 (3_level) 4F1 (3_level) GND FS (3_level) VCCN REFB+ F 4QB0 VCCN 3DS1 (3_level) GND GND GND GND FBF0 (3_level) VCCN 2QA0 G 4QA1 2DS1 (3_level) VCCQ GND GND GND GND VCCQ 1F0 (3_level) 2QA1 H 4QA0 1DS1 (3_level) 1DS0 (3_level) VCCQ GND GND VCCQ OUTPUT MODE (3_level) FBDIS 2QB0 J 4DS0 (3_level) 3DS0 (3_level) 2DS0 (3_level) DIS1 VCCN VCCN GND INV3 (3_level) DIS3 2QB1 K 2F1 (3_level) 1F1 (3_level) DIS2 VCCN 3QA0 3QA1 GND 3QB0 3QB1 DIS4 [+] Feedback |
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