CY2XP31

Document #: 001-06385 Rev. *H

Page 6 of 10

Application Information

Power Supply Filtering Techniques

As in any high speed analog circuitry, noise at the power supply

pins can degrade performance. To achieve optimum jitter perfor-

mance, use good power supply isolation practices. Figure 9 illus-

trates a typical filtering scheme. Because all of the current flows

through pin 1, the resistance and inductance between this pin

and the supply is minimized. A 0.01 or 0.1 µF ceramic chip

capacitor is also located close to this pin to provide a short and

low impedance AC path to ground. A 1 to 10 µF ceramic or

tantalum capacitor is located in the general vicinity of this device

and may be shared with other devices.

Figure 9. Power Supply Filtering

Termination for LVPECL Output

The CY2XP31 implements its LVPECL driver with a current

steering design. For proper operation, it requires a 50 ohm dc

termination on each of the two output signals. For 3.3 V

operation, this data sheet specifies output levels for termination

Note that it is also possible to terminate with 50 ohms to ground

values. Termination resistors are best located close to the desti-

nation device. To avoid reflections, trace characteristic

Figure 10 shows a standard termination scheme.

Figure 10. LVPECL Output Termination

Crystal Input Interface

The CY2XP31 is characterized with 18 pF parallel resonant

crystals. The capacitor values shown in Figure 11 are deter-

mined using a 25 MHz 18 pF parallel resonant crystal and are

chosen to minimize the ppm error. Note that the optimal values

for C1 and C2 depend on the parasitic trace capacitance and are

therefore layout dependent.

Figure 11. Crystal Input Interface

3.3V

10µF

0.1μF

VDD

V DD

0.01 µF

(Pin 1)

(Pin 8)

CLK

84

Ω

84

Ω

Z0 = 50

Ω

Z0 = 50

Ω

3.3V

125

Ω

125

Ω

IN

CLK#

Device

XIN

XOUT

X1

18 pF Parallel

Crystal

C1

33 pF

C2

27 pF

[+] Feedback