CY2DP1502

1:2 LVPECL Fanout Buffer

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 001-56308 Rev. *G

Revised April 19, 2011

Features

pair distributed to two LVPECL output pairs

(12-kHz to 20-MHz offset)

small outline package (TSSOP) package

[1]

Functional Description

The

CY2DP1502

is

an

ultra-low

noise,

low-skew,

low-propagation delay 1:2 LVPECL fanout buffer targeted to

meet

the

requirements

of

high-speed

clock

distribution

applications. The device has a fully differential internal

architecture that is optimized to achieve low additive jitter and

low skew at operating frequencies of up to 1.5 GHz.

Note

1. Input AC-coupling capacitors are required for voltage-translation applications.

Logic Block Diagram

Q0

Q0#

Q1

Q1#

IN

IN#