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ISL61852KCRZ Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL61852KCRZ Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 20 page ISL6185 5 FN6937.1 June 27, 2011 Pin Configurations ISL6185 (8 LD SOIC/DFN) TOP VIEW ISL6185 (10 LD DFN) TOP VIEW 1 2 3 4 8 7 6 5 VIN OUT1 OUT2 FLT1 FLT2 GND (GND) EPAD DFN Only EN1/EN1 EN2/EN2 1 2 3 4 10 9 8 7 VIN OUT1 OUT2 FLT1 FLT2 GND (GND) EPAD 5 6 VIN NC EN1/EN1 EN2/EN2 Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 8 Ld SOIC/DFN 10 Ld DFN 1 1 GND IC ground reference. 2 2, 3 VIN Chip bias, Controlled Voltage Input, Undervoltage Lock Out (UVLO). VIN provides chip bias voltage. At VIN < 1.7V chip functionality is disabled, FLT is active and floating, and OUT is held low. Range 0V to 5.5V. 3, 4 4, 5 EN1, EN1/ EN2, EN2 Enable/Disable inputs, Active high (EN) and active low (EN) options enable the power switch. These inputs have internal 1M Ω pull-off resistors. Range 0V to VIN. 5, 8 6, 10 FLT2 FLT1 Overcurrent Fault Indicator. FLT floats and is disabled until VIN >VUVLO. This output is pulled low after the current limit time-out period has expired. Fault is not signaled due to over-temperature shut down. Range 0V to VIN. 6, 7 7, 9 OUT2, OUT1 Controlled Supply Output. Upon an OC condition, IOUT is current limited. Current limit response time is within 200µs. This output remains in current limit for a nominal 12ms before being turned off either for the latch or auto retry versions. Range 0V to VIN. - 8 NC This pin is not electrically connected internally. PD (DFN only) PD EPAD Thermal Dissipation Exposed PAD Range: Connect to GND. |
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