ISL6328

6

FN7621.1

June 7, 2011

OCP

10

A capacitor from this pin to ground determines the time that the regulator is allowed to service a load

current spike that exceeds the internal OCP trip point.

TCOMP1, TCOMP2

11, 12

These two pins are used to compensate the inductor current sensing for fluctuations due to

temperature.

RGND

13

Inverting input to the Core and Northbridge regulator precision differential remote-sense amplifiers. This

pin should be connected to the remote ground sense pin of the processor core, VSS_SENSE.

VSEN

14

Non-inverting input to the Core regulator precision differential remote-sense amplifier. This pin should be

connected to the remote Core sense pin of the processor, VDD_SENSE.

FB_PSI

15

In PSI mode this pin is internally shorted to the FB pin to augment the feedback compensation network

for the lower phase count.

FB

16

Inverting input to the internal error amplifier for the Core regulator.

COMP

17

Output of the internal error amplifier for the Core regulator.

FS

18

This is a dual function pin. A resistor, placed from FS to either Ground or VCC sets the switching

frequency of both controllers. Refer to Equation 1 for proper resistor calculation.

This pin also controls the SVID high and low trip thresholds.

APA

19

Allows for programming of the Auto Phase Alignment threshold. A resistor in parallel with a capacitor

to ground is used to set this threshold.

ISENn+, ISENn-,

ISEN_NB+, ISEN_NB-

20, 21, 22,

23, 43, 44,

45, 46, 47,

48

These pins are used for differentially sensing the corresponding channel output currents. The sensed

currents are used for channel balancing, protection, and core load line regulation.

Connect ISEN- to the node between the RC sense elements surrounding the inductor of the respective

across the sense capacitor is proportional to the inductor current. The sense current, therefore, is

PHASE1,

PHASE2

33,

24

Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path

for the upper MOSFET drives.

GND

49

Bias and reference ground for the IC. The GND connection for the ISL6328 is made with three pins and

through the thermal pad on the bottom of the package.

EN

25

This pin is a threshold-sensitive (approximately 0.85V) system enable input for the controller. Held low, this

pin disables both CORE and NB controller operation. Pulled high, the pin enables both controllers for

operation.

A second function of this pin is to provide driver bias monitor for external drivers. A resistor divider with the

center tap connected to this pin from the drive bias supply prevents enabling the controller before

insufficient bias is provided to external driver. The resistors should be selected such that when the POR-trip

point of the external driver is reached, the voltage at this pin meets the above mentioned threshold level.

UGATE1, UGATE2

32, 26

Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled gate

drive for the upper MOSFET and is monitored for shoot-through prevention purposes.

BOOT1, BOOT2

31, 27

This pin provides the bias voltage for the corresponding upper MOSFET drive. Connect this pin to

appropriately-chosen external bootstrap capacitor. The internal bootstrap diode connected to the PVCC

pin provides the necessary bootstrap charge.

LGATE1, LGATE2

30, 28

Connect this pin to the corresponding MOSFET’s gate. This pin provides the PWM-controlled gate drive

for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to

determine when the lower MOSFET has turned off.

GVOT

29

The power supply pin for the multi-phase internal MOSFET drivers. In normal operation, this pin is

shorted to the PVCC pin. While in PSI mode, this pin is tied to the output of the internal LDO for Gate

Drive Voltage Optimization. Decouple this pin with a quality 2.2

μF ceramic capacitor.

VDDPWRGD

34

During normal operation this pin indicates whether both output voltages are within specified overvoltage

and undervoltage limits. If either output voltage exceeds these limits or a reset event occurs (such as an

overcurrent event), the pin is pulled low. This pin is always low prior to the end of soft-start.

PIN NAME

PIN NUMBER

DESCRIPTION

(EQ. 1)

10

10.61 1.035

fs

()

log

–

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