PD671xxx - 8 / 12 / 24-Channel PoE AF and AT DIMM

Data Sheet (Non-confidential)

Copyright © 2009

Microsemi

Page 7

Rev. 1.0 / 17-March-10

Analog Mixed Signal Group

2381 Morse Avenue, Irvine, CA 92614, USA; Within the USA: (800) 713-4113, Outside the USA: (949) 221-7100 Fax: (949) 756-0308

Pin Description

Signals are categorized as ‘analog’ (input or output) or ‘digital’ (input, output and I/O).

Pin

Pin Name

Pin Type

Pin Description

Pin

Pin

Name

Pin Type

Pin Description

1

85

2

86

3

87

4

88

5

89

6

Vmain

Main V+ input

90

Vmain

Main V+ input

7

91

8

92

9

93

10

94

11

95

12

Vmain_ret

Power input

Main V return

96

Vmain_ret

Power input

Main V return

13

Port_P0

Channel 1 positive output

97

14

Port_N0

Channel 1 negative output

98

15

Port_P1

Channel 2 positive output

99

16

Port_N1

Channel 2 negative output

100

17

Port_P2

Channel 3 positive output

101

18

Port_N2

Channel 3 negative output

102

19

Port_P3

Channel 4 positive output

103

20

Port_N3

Channel 4 negative output

104

21

Port_P4

Channel 5 positive output

105

22

Port_N4

Channel 5 negative output

106

23

Port_P5

Channel 6 positive output

107

24

Port_N5

Channel 6 negative output

108

25

Port_P6

Channel 7 positive output

109

26

Port_N6

Channel 7 negative output

100

27

Port_P7

Channel 8 positive output

111

28

Port_N7

Channel 8 negative output

112

Spare

29

Port_P8

Channel 9 positive output

113

TBD

TBD

30

Port_N8

Channel 9 negative output

114

TBD

TBD

31

Port_P9

Channel 10 positive output

115

TBD

TBD

32

Port_N9

Channel 10 negative output

116

TBD

TBD

33

Port_P10

Channel 11 positive output

117

I2C_Addr_0

Digital input

Auto mode; sets I2C address

34

Port_N10

Channel 11 negative output

118

Qgnd0

Ground

Quiet ground

35

Port_P11

Channel 12 positive output

119

CP_0

Analog output NC (not in use)

36

Port_N11

Analog output

Channel 12 negative output

120

ASICINI_6_

Out

37

TBD

TBD

121

ASICINI_7_

Out

Analog output

Determine DIMM 4 managers

ESPI address

38

TBD

TBD

122

xExist

Digital output Grounded internally- DIMM is

present

39

ASICINI_4_

Out

123

Ext_reg

Analog output External regulation for 3.3 V

40

ASICINI_5_

Out

Analog output

Determine DIMM 3 managers

ESPI address

124

3_3Vout

Analog output 3.3 V output to support opto

couplers (5 V tolerant)

41

xLed_Cs

Digital output

CS for LED support

125

XHswp_On

Digital output Connect to MCU

42

TBD

TBD

126

DGND

Ground

Digital ground

43

BKGD

Digital input

Factory use only

127

SCK

Digital I/O

SPI clock – PD69012 internal

comm

44

DGND

Ground

Digital ground

128

MISO

Digital I/O

SPI I/O – PD69012 internal

comm

45

xAsic_Reset

Digital I/O

Internal reset to PD69012

129

MOSI

Digital I/O

SPI I/O – PD69012 internal

comm

46

xReset_In

Digital input

A reset signal driven by the

Host CPU to PoE DIMM

130

ASICINI_0_

In

Analog input

Determine DIMM managers

ESPI address

47

ASICINI_0_

Out

Analog output

Determine DIMM 1 manager

ESPI address

131

ASICINI_1_

In

Analog input

Determine DIMM managers

ESPI address

48

ASICINI_1_

Out

Analog output

Determine DIMM 1 managers

ESPI address

132

CS0

Digital I/O

CS for ESPI

49

ASICINI_2_

Out

Analog output Determine DIMM 2 managers

ESPI address

133

DGND

Ground

Digital ground