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CY8CLED08 Datasheet(PDF) 10 Page - Cypress Semiconductor |
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CY8CLED08 Datasheet(HTML) 10 Page - Cypress Semiconductor |
10 / 52 page CY8CLED08 Document Number: 001-12981 Rev. *J Page 10 of 52 LEGEND: A = Analog, I = Input, and O = Output. 6. Register Reference This section lists the registers of the CY8CLED08 EZ-Color device. 6.1 Register Conventions The register conventions specific to this section are listed in the following table. 6.2 Register Mapping Tables The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set to 1, the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. 45 I/O I/O P0[3] Analog column mux input and column output. 46 I/O I P0[1] Analog column mux input. 47 I/O P2[7] 48 I/O P2[5] Table 5-1. 48-Pin Part Pinout (QFN)[1] Convention Description R Read register or bit(s) W Write register or bit(s) L Logical register or bit(s) C Clearable register or bit(s) # Access is bit specific Table 6-1. Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access PRT0DR 00 RW 40 ASC10CR0 80 RW C0 PRT0IE 01 RW 41 ASC10CR1 81 RW C1 PRT0GS 02 RW 42 ASC10CR2 82 RW C2 PRT0DM2 03 RW 43 ASC10CR3 83 RW C3 PRT1DR 04 RW 44 ASD11CR0 84 RW C4 PRT1IE 05 RW 45 ASD11CR1 85 RW C5 PRT1GS 06 RW 46 ASD11CR2 86 RW C6 PRT1DM2 07 RW 47 ASD11CR3 87 RW C7 PRT2DR 08 RW 48 ASC12CR0 88 RW C8 PRT2IE 09 RW 49 ASC12CR1 89 RW C9 PRT2GS 0A RW 4A ASC12CR2 8A RW CA PRT2DM2 0B RW 4B ASC12CR3 8B RW CB PRT3DR 0C RW 4C ASD13CR0 8C RW CC PRT3IE 0D RW 4D ASD13CR1 8D RW CD PRT3GS 0E RW 4E ASD13CR2 8E RW CE PRT3DM2 0F RW 4F ASD13CR3 8F RW CF PRT4DR 10 RW 50 ASD20CR0 90 RW D0 PRT4IE 11 RW 51 ASD20CR1 91 RW D1 PRT4GS 12 RW 52 ASD20CR2 92 RW D2 PRT4DM2 13 RW 53 ASD20CR3 93 RW D3 PRT5DR 14 RW 54 ASC21CR0 94 RW D4 PRT5IE 15 RW 55 ASC21CR1 95 RW D5 PRT5GS 16 RW 56 ASC21CR2 96 RW I2C_CFG D6 RW PRT5DM2 17 RW 57 ASC21CR3 97 RW I2C_SCR D7 # 18 58 ASD22CR0 98 RW I2C_DR D8 RW 19 59 ASD22CR1 99 RW I2C_MSCR D9 # 1A 5A ASD22CR2 9A RW INT_CLR0 DA RW 1B 5B ASD22CR3 9B RW INT_CLR1 DB RW 1C 5C ASC23CR0 9C RW DC 1D 5D ASC23CR1 9D RW INT_CLR3 DD RW 1E 5E ASC23CR2 9E RW INT_MSK3 DE RW Blank fields are Reserved and should not be accessed. # Access is bit specific. |
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