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LX1681CDM-TR Datasheet(PDF) 7 Page - Microsemi Corporation |
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LX1681CDM-TR Datasheet(HTML) 7 Page - Microsemi Corporation |
7 / 9 page Microsemi Linfinity Microelectronics Division 11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570 Page 7 Copyright © 2000 Rev. 1.1b,2005-03-09 LX1681/1682 Voltage-Mode PWM Controllers PRODUCTION DATA SHEET TM ® APPLI CATI ON I N FORMATI O N FET SELECTION (continued) Synchronous Rectification – Lower MOSFET The lower pass element can be either a MOSFET or a Schottky diode. The use of a MOSFET (synchronous rectification) will result in higher efficiency, but at higher cost than using a Schottky diode (non-synchronous). Power dissipated in the bottom MOSFET will be: [] W Cycle Duty R I P ON DS D 51 . 3 1 ) ( 2 = − × × = [IRL3303 or 1.76W for the IRL3102] Non-Synchronous Operation - Schottky Diode A typical Schottky diode, with a forward drop of 0.6V will dissipate 0.6 * 15 * [1 – 2/5] = 5.4W (compared to the 1.8 to 3.5W dissipated by a MOSFET under the same conditions). This power loss becomes much more significant at lower duty cycles. The use of a dual Schottky diode in a single TO-220 package (e.g. the MBR2535) helps improve thermal dissipation. Operation From A Single Power Supply The LX1681/1682 needs a secondary supply voltage (VC1) to provide sufficient drive to the upper MOSFET. In many applications with a 5V (VCC) and a 12V (VC1) supply are present. In situations where only 5V is present, VC1 can be generated using a bootstrap (charge pump) circuit, as shown in Figure 4 (Typical Applications section). The capacitor (C4) is alternatively charged up from VCC via the Schottky diode (D2), and then boosted up when the FET is turned on. This scheme provides a VC1 voltage equal to 2 * VCC - VDS (D2), or approximately 9.5V with VCC = 5V. This voltage will provide sufficient gate drive to the external MOSFET in order to get a low RDS(ON) . Note that using the bootstrap circuit in synchronous rectification mode is likely to result in faster turn-on than in non-synchronous mode. LAYOUT GUIDELINES - THERMAL DESIGN A great deal of time and effort were spent optimizing the thermal design of the demonstration boards. Any user who intends to implement an embedded motherboard would be well advised to carefully read and follow these guidelines. If the FET switches have been carefully selected, external heatsinking is generally not required. However, this means that copper trace on the PC board must now be used. This is a potential trouble spot; as much copper area as possible must be dedicated to heatsinking the FET switches, and the diode as well if a non-synchronous solution is used. In our VRM module, heatsink area was taken from internal ground and VCC planes which were actually split and connected with VIAS to the power device tabs. The TO-220 and TO-263 cases are well suited for this application, and are the preferred packages. Remember to remove any conformal coating from all exposed PC traces which are involved in heatsinking. LX168x 5V Input O utput GND FIGURE 2 — Enabling Linear Regulator General Notes As always, be sure to provide local capacitive decoupling close to the chip. Be sure use ground plane construction for all high- frequency work. Use low ESR capacitors where justified, but be alert for damping and ringing problems. High-frequency designs demand careful routing and layout, and may require several iterations to achieve desired performance levels. Power Traces To reduce power losses due to ohmic resistance, careful consid- eration should be given to the layout of traces that carry high currents. The main paths to consider are: Input power from 5V supply to drain of top MOSFET. Trace between top MOSFET and lower MOSFET or Schottky diode. Trace between lower MOSFET or Schottky diode and ground. Trace between source of top MOSFET and inductor and load. All of these traces should be made as wide and thick as possible, in order to minimize resistance and hence power losses. It is also recommended that, whenever possible, the ground, input and output power signals should be on separate planes (PCB layers). See Figure 2 – bold traces are power traces. Layout Assistance Please contact Linfinity’s Applications Engineers for assistance with any layout or component selection issues. A Gerber file with layout for the most popular devices is available upon request. Evaluation boards are also available upon request. Please check Linfinity's web site for further application notes. |
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