VBST

SW3

SW1

SW2

VFB

VREG5

GND

SS

POWER PAD

16

7

5

6

2

3

4

1

15

12

11

9

8

10

14

13

POWER PAD

SW1

VBST

SS

VO

VFB

GND

PGND1

14

7

5

6

2

3

4

1

VIN2

EN

PG

VREG5

13

12

11

9

8

PGND2

10

SW2

VIN1

TPS54429E

www.ti.com

SLVSAS0 –FEBRUARY 2011

RSA PACKAGE

DEVICE INFORMATION

(TOP VIEW)

PWP PACKAGE

(TOP VIEW)

PIN FUNCTIONS

PIN

DESCRIPTION

NAME

NUMBER

PWP 14

RSA 16

VO

1

16

Connect to output of converter. This terminal is used for On-Time Adjustment.

VFB

2

1

Converter feedback input. Connect to output voltage with feedback resistor divider.

5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not

VREG5

3

2

active when EN is low.

SS

4

3

Soft-start control. A external capacitor should be connected to GND.

GND

5

4

Signal ground pin.

PG

6

5

Open drain power good output.

EN

7

6

Enable control input. EN is active high and must be pulled up to enable the device.

PGND1,

Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect

8, 9

7, 8

PGND2

PGND and GND strongly together near the IC.

Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to

SW1, SW2

10, 11

9, 10, 11 current comparators.

Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to

VBST

12

12

respective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST pin.

Power input and connected to high side NFET drain. Supply input for 5-V internal linear regulator

VIN1, VIN2

13, 14

13, 14, 15 for the control circuitry.

PowerPAD™

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be

or Thermal

Back side Back side connected to PGND.

Pad

©

2011, Texas Instruments Incorporated

5

Product Folder Link(s) :TPS54429E