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TPS40322 Datasheet(PDF) 11 Page - Texas Instruments

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Part # TPS40322
Description  Dual Output or Two-Phase Synchronous Buck Controller
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS40322 Datasheet(HTML) 11 Page - Texas Instruments

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TPS40322
www.ti.com
SLUSAF8
– JUNE 2011
PIN FUNCTIONS (continued)
NAME
PIN
I/O
DESCRIPTION
Bootstrapped gate drive output for the high-side N-channel MOSFET for CH2. A 2-
Ω resistor is
HDRV2
16
O
recommended for a noisy environment.
Used to set the overcurrent limit for CH1 with 10
μA of current flowing through a resistor from this pin to
ILIM1
30
I
AGND.
Used to set the overcurrent limit for CH2 with 10
μA of current flowing through a resistor from this pin to
ILIM2/VSNS
11
I
AGND. In multi-phase mode, this pin becomes VSNS as the positive terminal of a remote sense amplifier.
LDRV1
22
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH1.
LDRV2
18
O
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for CH2.
PG1
27
O
Open drain power good indicator for CH1 output voltage.
PG2
14
O
Open drain power good indicator for CH2 output voltage.
Power ground 1. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce
PGND1
21
-
channel to channel interference.
Power ground 2. Separate power ground for CH1 and CH2 in the PCB layout could potentially reduce
PGND2
19
-
channel to channel interference.
Used to set master or slave mode and phase angles. The master emits a 50% duty clock to the slave. The
PHSET
32
I
slave synchronizes to the external clock and select the phase shift angle.
RT
2
I
Connect a resistor from this pin to AGND to set the oscillator frequency.
SW1
23
I
Connect to the switched node on converter CH1. It is the return for the CH 1 high-side gate driver.
SW2
17
I
Connect to the switched node on converter CH2. It is the return for the CH 2 high-side gate driver.
In master mode, a 2x free running frequency clock is sent out on SYNC pin.
In slave mode, sync to an external clock which is
±20% of the free running MASTER_CLOCK frequency.
SYNC
1
I/O
The MASTER_CLOCK frequency is 2x of the free running frequency (set by RT) and operates at 50% duty
cycle.
UVLO
31
I
A resistor divider from VIN determines the input voltage that the controller starts.
Power input to the controller. A low ESR bypass ceramic capacitor of 0.1
μF or greater should be
VDD
26
I
connected closely from this pin to AGND.
Copyright
© 2011, Texas Instruments Incorporated
11


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