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CSD97370Q5M Datasheet(PDF) 12 Page - Texas Instruments

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Part No. CSD97370Q5M
Description  Synchronous Buck NexFET Power Stage
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
Logo TI1 - Texas Instruments

CSD97370Q5M Datasheet(HTML) 12 Page - Texas Instruments

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– JUNE 2011 – REVISED JUNE 2011
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
Electrical Performance
The CSD97370Q5M has the ability to switch at voltages rates greater than 10kV/
µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.
The placement of the input capacitors relative to VIN and PGND pins of CSD97370Q5M device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 20).
The example in Figure 20 uses 6 x 10
µF 1206 25V ceramic capacitors (TDK Part # C3216X5R1C106KT or
equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of
vias interconnecting both layers. In terms of priority of placement next to the Power Stage C5, C8 and C7,
C19 should follow in order.
The bootstrap cap CBOOT 0.1µF 0603 16V ceramic capacitor should be closely connected between BOOT and
BOOT_R pins
The switching node of the output inductor should be placed relatively close to the Power Stage
CSD97370Q5M VSW pins. Minimizing the VSW node length between these two components will reduce the
PCB conduction losses and actually reduce the switching noise level.(1)
Thermal Performance
The CSD97370Q5M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
Use the smallest drill size allowed in your design. The example in Figure 20 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user
’s PCB design rules and
manufacturing capabilities.
Figure 20. Recommended PCB Layout (Top Down View)
Keong W. Kam, David Pommerenke,
“EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
– Rolla
© 2011, Texas Instruments Incorporated

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