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MC68LC302 Datasheet(PDF) 19 Page - Motorola, Inc |
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MC68LC302 Datasheet(HTML) 19 Page - Motorola, Inc |
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19 / 169 page  Configuration, Clocking, Low Power Modes, and Internal Memory Map 2-6 MC68LC302 REFERENCE MANUAL MOTOROLA changed according to the description below. Several control bits are still available but have new locations. The low power modes on the MC68302 have changed completely and will be discussed later in 2.4.4.1 IMP Low Power Modes. 2.4.1.1 CLOCK CONTROL REGISTER. The clock control register address $FA is not implemented on the MC68LC302. This register location has been reassigned to the IOMCR and ICKCR registers. The clock control register bits have been reassigned as follows: CLKO Drive Options (CLKOMOD1–2) These bits are now in the IMP clock control register (IPLCR) on the MC68LC302, see 2.4.3.4.2 IMP PLL and Clock Control Register (IPLCR). Three-State TCLK1 (TSTCLK1) This bit is now in the DISC register on the MC68LC302, see 4.3.2 Disable SCC1 Serial Clocks Out (DISC). Three-State RCLK1 (TSRCLK1) This bit is now in the DISC register on the MC68LC302, see 4.3.2 Disable SCC1 Serial Clocks Out (DISC). Disable BRG1 (DISBRG1) This bit has been removed since the BRG1 pin was removed. 2.4.2 MC68LC302 System Clock Generation Figure 2-3, the MC68LC302 system clock schematic, shows the IMP clock synthesizer. The block includes an on-chip oscillator, a clock synthesizer, and a low-power divider, which allows a comprehensive set of options for generating the system clock. The choices offer many opportunities to save power and system cost, without sacrificing flexibility and control. In addition to performing frequency multiplication, the PLL block can also provide EXTAL to CLKO skew elimination, and dynamic low power divides of the output PLL system clock. Clock source and default settings are determined during the reset of the IMP. The MC68LC302 decodes the MODCLK and VCCSYN pins and the value of these pins deter- mines the initial clocking for the part. Further changes to the clocking scheme can be made by software. After reset, the 68000 core can control the IMP clocking through the following registers: 1. IMP Operation Mode Control Register, IOMCR (2.4.4.1.6 IMP Operation Mode Control Register (IOMCR)). 2. IMP PLL and Clock Control Register, IPLCR (2.4.3.4 Frequency Multiplication). 3. IMP Interrupt Wake-Up Control Register, IWUCR (2.4.4.2.4 IMP Wake-Up Control Register (IWUCR)). 4. Periodic Interrupt Timer Register, PITR (See Section 3 System Integration Block (SIB) ). |
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