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MC68LC302 Datasheet(PDF) 6 Page - Motorola, Inc

Part No. MC68LC302
Description  Low Power Integrated Multiprotocol Processor Reference Manual
Download  169 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68LC302 Datasheet(HTML) 6 Page - Motorola, Inc

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Table of Contents
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Title
Page
Number
Number
MOTOROLA
MC68LC302 REFERENCE MANUAL
vii
3.6
Parallel I/O Ports ................................................................................... 3-17
3.6.1
Parallel I/O Port Differences.................................................................. 3-17
3.6.2
Port A .................................................................................................... 3-17
3.6.3
Port B .................................................................................................... 3-18
3.6.3.1
PB7–PB3............................................................................................... 3-18
3.6.3.2
PB11–PB8............................................................................................. 3-18
3.6.4
Port N .................................................................................................... 3-19
3.6.5
Port Registers........................................................................................ 3-19
3.7
Timers ................................................................................................... 3-20
3.7.1
MC68LC302 General Purpose Timer Difference .................................. 3-20
3.7.2
General Purpose Timers Programming Mode....................................... 3-20
3.7.2.1
Timer Mode Register (TMR1, TMR2).................................................... 3-20
3.7.2.2
Timer Reference Registers (TRR1, TRR2) ........................................... 3-21
3.7.2.3
Timer Capture Registers (TCR1, TCR2) ............................................... 3-21
3.7.2.4
Timer Counter (TCN1, TCN2) ............................................................... 3-21
3.7.2.5
Timer Event Registers (TER1, TER2) ................................................... 3-21
3.7.3
Timer 3 - Software Watchdog Timer ..................................................... 3-22
3.7.3.1
Software Watchdog Reference Register (WRR) ................................... 3-22
3.7.3.2
Software Watchdog Counter (WCN) ..................................................... 3-22
3.7.4
Periodic Interrupt Timer (PIT)................................................................ 3-22
3.7.4.1
Overview ............................................................................................... 3-23
3.7.4.2
Periodic Timer Period Calculation ......................................................... 3-23
3.7.4.3
Using the Periodic Timer As a Real-Time Clock ................................... 3-24
3.7.4.4
Periodic Interrupt Timer Register (PITR)............................................... 3-24
3.8
External Chip-Select Signals and Wait-State Logic .............................. 3-25
3.8.1
Chip-Select Registers............................................................................ 3-26
3.8.1.1
Base Register (BR3–BR0) .................................................................... 3-26
3.8.1.2
Option Registers (OR3–OR0) ............................................................... 3-26
3.8.2
Disable CPU Logic (M68000)................................................................ 3-28
3.8.3
Bus Arbitration Logic ............................................................................. 3-28
3.8.3.1
Internal Bus Arbitration.......................................................................... 3-28
3.8.3.2
External Bus Arbitration......................................................................... 3-28
3.9
Dynamic RAM Refresh Controller ......................................................... 3-29
Section 4
Communications Processor (CP)
4.1
MC68LC302 Key Differences from the MC68302 ................................... 4-1
4.2
Serial Channels Physical Interface.......................................................... 4-2
4.2.1
Serial Interface Registers ........................................................................ 4-2
4.2.1.1
Serial Interface Mode Register (SIMODE) .............................................. 4-2
4.2.1.2
Serial Interface Mask Register (SIMASK) ............................................... 4-4
4.3
Serial Communication Controllers (SCCs) .............................................. 4-4
4.3.1
SCC Configuration Register (SCON) ...................................................... 4-4
4.3.1.1
Divide by 2 Input Blocks (New Feature) .................................................. 4-4
4.3.2
Disable SCC1 Serial Clocks Out (DISC) ................................................. 4-4
4.3.2.1
RCLK1 and TCLK1 Pin Options .............................................................. 4-5


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