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MC68HC705C8A Datasheet(PDF) 64 Page - Motorola, Inc |
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MC68HC705C8A Datasheet(HTML) 64 Page - Motorola, Inc |
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64 / 222 page  Technical Data MC68HC705C8A — Rev. 2.0 64 Resets MOTOROLA Resets 5.3.3.2 Non-Programmable COP Watchdog A timeout of the 18-stage ripple counter in the non-programmable COP watchdog generates a reset. The timeout period is 65.536 ms when fOSC = 4 MHz. The timeout period for the non-programmable COP timer is a direct function of the crystal frequency. The equation is: Two memory locations control operation of the non-programmable COP watchdog: 1. Non-programmable COP enable bit (NCOPE) in mask option register 2 (MOR2) Programming the NCOPE bit in MOR2 to a logic 1 enables the non-programmable COP watchdog. See 9.5.3 Mask Option Register 2. NOTE: Writing a logic 1 to the programmable COP enable bit (PCOPE) in the COP control register enables the programmable COP watchdog. Setting the PCOPE bit while the NCOPE bit is programmed to logic 1 enables both COP watchdogs to operate at the same time. Table 5-1. Programmable COP Timeout Period Selection CM1:CM0 COP Timeout Rate Programmable COP Timeout Period fOSC = 4.0 MHz fOP = 2.0 MHz fOSC = 3.5795 MHz fOP = 1.7897 MHz fOSC = 2.0 MHz fOP = 1.0 MHz fOSC = 1.0 MHz fOP = 0.5 MHz 00 fOP ÷ 2 15 16.38 ms 18.31 ms 32.77 ms 65.54 ms 01 fOP ÷ 2 17 65.54 ms 73.24 ms 131.07 ms 262.14 ms 10 fOP ÷ 2 19 262.14 ms 292.95 ms 524.29 ms 1.048 s 11 fOP ÷ 2 21 1.048 s 1.172 s 2.097 s 4.194 s 262,144 fOSC Timeout period = |
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