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ADF7023-J Datasheet(PDF) 54 Page - Analog Devices |
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ADF7023-J Datasheet(HTML) 54 Page - Analog Devices |
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54 / 100 page  ADF7023-J Rev. 0 | Page 54 of 100 LOW POWER MODES The ADF7023-J can be configured to operate in a broad range of energy sensitive applications where battery lifetime is critical. This includes support for applications where the ADF7023-J is required to operate in a fully autonomous mode or applications where the host processor controls the transceiver during low power mode operation. These low power modes are implemented using a hardware wake-up controller (WUC), a firmware timer, and the smart wake mode functionality of the on-chip communications processor. The hardware WUC is a low power WUC that comprises a 16-bit wake-up timer with a programmable prescaler. The 32.768 kHz RCOSC or XOSC provides the clock source for the timer. The firmware timer is a software timer residing on the ADF7023-J. The firmware timer is used to count the number of WUC timeouts and can be used to count the number of ADF7023-J wake-ups. The WUC and the firmware timer, therefore, provide a real-time clock capability. Using the low power WUC and the firmware timer, the SWM firmware allows the ADF7023-J to wake up autonomously from sleep without intervention from the host processor. During this wake-up period, the ADF7023-J is controlled by the communi- cations processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby dramatically reducing overall system current consumption. The smart wake mode can then wake the host processor on an interrupt condition. An overview of the low power mode configuration is shown in Figure 69, and the register settings that are used for the various low power modes are described in Table 28. Table 28. Settings for Low Power Modes Low Power Mode Memory Address Register Name Bit Description Deep Sleep Modes 0x30D1 WUC_CONFIG_LOW WUC_BBRAM_EN 0: BBRAM contents are not retained during PHY_SLEEP. 1: BBRAM contents are retained during PHY_SLEEP. WUC 0x30C1 WUC_CONFIG_HIGH WUC_PRESCALER[2:0] Sets the prescaler value of the WUC. WUC 0x30D1 WUC_CONFIG_LOW WUC_RCOSC_EN Enables the 32.768 kHz RC OSC. WUC 0x30D1 WUC_CONFIG_LOW WUC_XOSC32K_EN Enables the 32.768 kHz external OSC. WUC 0x30D1 WUC_CONFIG_LOW WUC_CLKSEL Sets the WUC clock source. 1: RC OSC selected. 2: XOSC selected. WUC 0x30D1 WUC_CONFIG_LOW WUC_ARM Enable to ensure that the device wakes from the PHY_SLEEP state on a WUC timeout. WUC 0x30E2, WUC_VALUE_HIGH WUC_TIMER_VALUE[15:0] The WUC timer value. 0x30F2 WUC_VALUE_LOW WUC Interval(s) = WUC_TIMER_VALUE × 32,768 1) ( 2 + LER WUC_PRESCA WUC 0x101 INTERRUPT_MASK_1 WUC_TIMEOUT Enables the interrupt on a WUC timeout. Firmware Timer 0x100 INTERRUPT_MASK_0 INTERRUPT_NUM_WAKEUPS Enabling this interrupt enables the firmware timer. Interrupt is set when the NUMBER_OF WAKEUPS count exceeds the threshold. Firmware Timer 0x102, 0x103 NUMBER_OF_WAKEUPS_0 NUMBER_OF_WAKEUPS_1 NUMBER_OF_WAKEUPS[15:0] Number of ADF7023-J wake-ups. Firmware Timer 0x104, 0x105 NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD_0 NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD_1 NUMBER_OF_WAKEUPS_IRQ_ THRESHOLD[15:0] Threshold for the number of ADF7023-J wake-ups. When exceeded, the ADF7023-J exits low power mode. SWM 0x11A MODE_CONTROL SWM_EN Enables smart wake mode. SWM 0x11A MODE_CONTROL SWM_RSSI_QUAL Enables RSSI prequalification in smart wake mode. |
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