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AD6643 Datasheet(PDF) 8 Page - Analog Devices

Part # AD6643
Description  Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6643 Datasheet(HTML) 8 Page - Analog Devices

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AD6643
Rev. 0 | Page 8 of 36
SWITCHING SPECIFICATIONS
Table 4.
Parameter
Symbol
Temperature
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
625
MHz
Conversion Rate1
Full
40
200
MSPS
CLK Period—Divide-by-1 Mode2
tCLK
Full
4.0
ns
CLK Pulse Width High2
tCH
Divide-by-1 Mode, DCS Enabled
Full
2.25
2.5
2.75
ns
Divide-by-1 Mode, DCS Disabled
Full
2.375
2.5
2.625
ns
Divide-by-2 Through Divide-by-8 Modes, DCS Enabled
Full
0.8
ns
DATA OUTPUT PARAMETERS (DATA, OR)
LVDS Mode
Data Propagation Delay2
tPD
Full
4.8
ns
DCO Propagation Delay2
tDCO
Full
5.5
ns
DCO to Data Skew2
tSKEW
Full
0.1
0.7
1.3
ns
Pipeline Delay (Latency)
Full
10
Cycles3
NSR Enabled
Full
13
Cycles3
Aperture Delay4
tA
Full
1.0
ns
Aperture Uncertainty (Jitter)4
tJ
Full
0.1
ps rms
Wake-Up Time (from Standby)
Full
10
μs
Wake-Up Time (from Power-Down)
Full
250
μs
OUT-OF-RANGE RECOVERY TIME
Full
3
Cycles
1 Conversion rate is the clock rate after the divider.
2 See
for timing diagram.
Figure 2
3 Cycles refers to ADC input sample rate cycles.
4 Not shown in timing diagrams.
TIMING SPECIFICATIONS
Table 5.
Parameter
Conditions
Min
Typ
Max
Unit
SYNC TIMING REQUIREMENTS
See Figure 3 for timing details
tSSYNC
SYNC to the rising edge of CLK setup time
0.3
ns
tHSYNC
SYNC to the rising edge of CLK hold time
0.4
ns
SPI TIMING REQUIREMENTS
See Figure 45 for SPI timing diagram
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
ns
tH
Hold time between CSB and SCLK
2
ns
tHIGH
Minimum period that SCLK should be in a logic high state
10
ns
tLOW
Minimum period that SCLK should be in a logic low state
10
ns
tEN_SDIO
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge (not shown in Figure 45)
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge (not shown in Figure 45)
10
ns


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