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PCA9663B Datasheet(PDF) 7 Page - NXP Semiconductors |
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PCA9663B Datasheet(HTML) 7 Page - NXP Semiconductors |
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7 / 66 page  PCA9663 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 1 — 6 June 2011 7 of 66 NXP Semiconductors PCA9663 Parallel bus to 3 channel Fm+ I2C-bus controller DATA until the entire sequence is loaded. If the transaction is a read transaction, the host must write a dummy byte (i.e., FFh) for each expected serial read byte to reserve the memory space in the buffer for the transaction. Care should be taken so as to not overflow the buffer with excessive read/write commands. In the event of an overflow, represented by the BE bit in the CTRLSTATUS register, will be set to logic 1. The INT pin will be set LOW if the BEMSK bit in the CTRLINTMSK register is logic 0. To recover the channel, a channel reset is required. All configuration and data needs to be checked by the host and resent to the I2C-bus controller. (See Section 7.3.2 “Buffer sizes”.) After sending all the commands and data it wanted to the I2C-bus controller, the host could either continue to program data for other channels or write to the CONTROL register to begin data transmission on the current channel. The transactions will be sent on the I2C-bus in the order in which the slave addresses are listed in the SLATABLE, separated by a RESTART condition. The last transaction in the sequence will end with a STOP condition. If during a READ command a NACK on the slave address is received, the buffer space allocated for the read will remain untouched and will contain the last information written in that location. A buffer read on the parallel bus should only be done after a valid buffer state is reached to guarantee data valid (see Section 7.5.1.1 “STATUS0_[n], STATUS1_[n], STATUS2_[n] — Transaction status registers”). A buffer write is only allowed during the channel idle state. To program data for another channel, that channel is selected and data programmed as described above. One or more channels can be busy while additional data is sent to the buffer of an idle channel. 7.3.1 Buffer management assumptions • Repeated STARTs will be sent between two consecutive transactions. • After the last operation on a channel is completed, a STOP will be sent. • In a READ transaction, after the last data byte has been received from a particular slave, a NACK is sent to the slave. 7.3.2 Buffer sizes The PCA9663 channels have individual buffers assigned to them. The contents of the buffers should only be modified during channel idle states. The memory allocation is 4352 bytes per channel. The buffer sizes represent the memory allocated for the data block only. The slave address table and configuration bytes are contained in other locations and do not need to be included in the required buffer size calculation. For example, to calculate the size of the memory needed to write 26 bytes to 10 slaves and to read 2 bytes from 4 slaves (no command bytes required for the read): 10 slaves 26 bytes/slave = 260 bytes for the write transactions 4 slaves 2bytes/slave = 8bytes for the read transactions A total of 268 bytes of buffer space is required to complete the sequence. |
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