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I.MX27 Datasheet(PDF) 94 Page - Freescale Semiconductor, Inc

Part # I.MX27
Description  Multimedia Applications Processor Multiple clock and power domains
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

I.MX27 Datasheet(HTML) 94 Page - Freescale Semiconductor, Inc

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i.MX27 and i.MX27L Data Sheet, Rev. 1.7
94
Freescale Semiconductor
Electrical Characteristics
NOTE
High is defined as 80% of signal value and low is defined as 20% of signal
value.
WE5
Clock rise/fall to RW Valid
0.90
2.60
ns
WE6
Clock rise/fall to RW Invalid
0.90
2.60
ns
WE7
Clock rise/fall to OE Valid
1.17
3.57
ns
WE8
Clock rise/fall to OE Invalid
1.17
3.57
ns
WE9
Clock rise/fall to EB[x] Valid
0.73
2.43
ns
WE10
Clock rise/fall to EB[x] Invalid
0.73
2.43
ns
WE11
Clock rise/fall to LBA Valid
1.03
2.84
ns
WE12
Clock rise/fall to LBA Invalid
1.03
2.84
ns
WE13
Clock rise/fall to Output Data Valid
1.04
4.01
ns
WE14
Clock rise to Output Data Invalid
1.04
4.01
ns
WE15
Input Data Valid to Clock rise, FCE=0 (in the case there is
ECB_B asserted during access)
1/2BCLK
+3.6
—ns
WE15
Input Data Valid to Clock rise, FCE=0 (in the case there is NO
ECB_B asserted during access)
6.95
ns
WE16
Cloc/k rise to Input Data Invalid, FCE=0
2.35
ns
WE17
Input Data Valid to Clock rise, FCE=1
1.24
ns
WE18
Clock rise to Input Data Invalid, FCE=1
0.23
ns
WE19
ECB setup time, FCE=0
7.23
ns
WE20
ECB hold time, FCE=0
2.93
ns
WE21
ECB setup time, FCE=1
1.08
ns
WE22
ECB hold time, FCE=1
0
ns
WE23
DTACK setup time
5.35
ns
WE24
DTACK hold time
3.19
ns
WE25
BCLK High Level Width1
3.0
ns
WE26
BCLK Low Level Width1
3.0
ns
WE27
BCLK Cycle time1
7.5
ns
Note:
1 BCLK parameters are being measured from the 50% point—that is, high is defined as 50% of signal
value and low is defined as 50% of signal value.
Table 50. WEIM Bus Timing Parameters (continued)
ID
Parameter
1.8 V
Unit
Min
Max


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