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ICE3AS02 Datasheet(PDF) 10 Page - Infineon Technologies AG |
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ICE3AS02 Datasheet(HTML) 10 Page - Infineon Technologies AG |
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10 / 22 page  F3 ICE3AS02 / ICE3AS02G / ICE3BS02 / ICE3BS02G Functional Description Version 1.2 10 02 Sep 2005 3.4 PWM Section Figure 7 PWM Section 3.4.1 Oscillator The oscillator generates a fixed frequency. The switching frequency for ICE3AS02/G is fOSC = 100kHz and for ICE3BS02/G fOSC = 67kHz. A resistor, a capacitor and a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed, in order to achieve a very accurate switching frequency. The ratio of controlled charge to discharge current is adjusted to reach a maximum duty cycle limitation of Dmax=0.72. 3.4.2 PWM-Latch FF1 The oscillator clock output provides a set pulse to the PWM- Latch when initiating the external Power Switch conduction. After setting the PWM-Latch can be reset by the PWM comparator, the Soft Start comparator or the Current-Limit comparator. In case of resetting, the driver is shut down immediately. 3.4.3 Gate Driver The Gate Driver is a fast totem pole gate drive which is designed to avoid cross conduction currents and which is equipped with a zener diode Z1 (see Figure 8) in order to improve the control of the Gate attached power transistors as well as to protect them against undesirable gate overvoltages. Figure 8 Gate Driver The driver-stage is optimized to minimize EMI and to provide high circuit efficiency. This is done by reducing the switch on slope when exceeding the external Power Switch threshold. This is achieved by a slope control of the rising edge at the driver’s output (see Figure 9). Figure 9 Gate Rising Slope Thus the leading switch on spike is minimized. When the external Power Switch is switched off, the falling shape of the driver is slowed down when reaching 2V to prevent an overshoot below ground. Furthermore the driver circuit is designed to eliminate cross conduction of the output stage. During powerup when VCC is below the undervoltage lockout threshold VVCCoff, the output of the Gate Driver is low to disable power transfer to the secondary side. Oscillator Duty Cycle max Gate Driver 0.72 Clock & G9 1 G8 PWM Section FF1 R S Q Gate Soft Start Comparator PWM Comparator Current Limiting Z1 VCC 1 PWM-Latch Gate t V Gate 5V C Load = 1nF ca. t = 130ns |
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