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SST39VF3201C Datasheet(PDF) 10 Page - Silicon Storage Technology, Inc |
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SST39VF3201C Datasheet(HTML) 10 Page - Silicon Storage Technology, Inc |
10 / 37 page ©2011 Silicon Storage Technology, Inc. DS25020A 06/11 10 32 Mbit Multi-Purpose Flash Plus SST39VF3201C / SST39VF3202C Preliminary Specifications A Microchip Technology Company Data# Polling (DQ7) When the SST39VF3201C/3202C are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 22 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector- , Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to ‘1’ if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro- gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 22 for a flowchart. Note: DQ7,DQ6 and DQ2 require a valid address when reading status information. Table 3: Write Operation Status Status DQ7 DQ6 DQ2 RY/BY# Normal Operation Standard Program DQ7# Toggle No Toggle 0 Standard Erase 0 Toggle Toggle 0 Erase-Suspend Mode Read from Erase-Sus- pended Sector/Block 1 1 Toggle 1 Read from Non- Erase- Suspended Sector/Block Data Data Data 1 Program DQ7# Toggle N/A 0 T3.0 25020 |
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