©2011 Silicon Storage Technology, Inc.

DS25020A

06/11

10

32 Mbit Multi-Purpose Flash Plus

SST39VF3201C / SST39VF3202C

Preliminary Specifications

A Microchip Technology Company

Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in

subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt

The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For

Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)

pulse. See Figure 8 for Data# Polling timing diagram and Figure 22 for a flowchart.

Toggle Bits (DQ6 and DQ2)

alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation

whether a particular sector is being actively erased or erase-suspended. Table 3 shows detailed status

Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 22 for a flowchart.

Table 3: Write Operation Status

Status

RY/BY#

Normal Operation

Standard Program

Toggle

No

Toggle

0

Standard Erase

0

Toggle

Toggle

0

Erase-Suspend

Mode

Read from Erase-Sus-

pended Sector/Block

1

1

Toggle

1

Read from Non- Erase-

Suspended Sector/Block

Data

Data

Data

1

Program

Toggle

N/A

0

T3.0 25020