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MC68302PV20 Datasheet(PDF) 44 Page - Motorola, Inc

Part No. MC68302PV20
Description  Integrated Multiprotocol Processor User’s Manual
Download  480 Pages
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC68302PV20 Datasheet(HTML) 44 Page - Motorola, Inc

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MC68000/MC68008 Core
2-14
MC68302 USER’S MANUAL
MOTOROLA
CFC—Compare Function Code
0 = The FC bits in the BAR are ignored. Accesses to the IMP 4K-byte block occur with-
out comparing the FC bits.
1 = The FC bits in the BAR are compared. The address space compare logic uses the
FC bits to detect address matches.
Bits 11–0—Base Address
The high address field is contained in bit 11–0 of the BAR. These bits are used to set the
starting address of the dual-port RAM. The address compare logic uses only the most sig-
nificant bits to cause an address match within its block size.
2.8 MC68302 MEMORY MAP
The following tables show the additional registers added to the M68000 to make up the
MC68302. All of the registers are memory-mapped. Four entries in the M68000 exception
vectors table (located in low RAM) are reserved for addresses of system configuration reg-
isters (see Table 2-6) that reside on-chip. These registers have fixed addresses of $0F0–
$0FF. All other on-chip peripherals occupy a 4K-byte relocatable address space. When an
on-chip register or peripheral is accessed, the internal access (IAC) pin is asserted.
*Reset only upon a total system reset.
The internal 1176-byte dual-port RAM has 576 bytes of system RAM (see Table 2-7) and
576 bytes of parameter RAM (see Table 2-8).
The parameter RAM contains the buffer descriptors for each of the three SCC channels, the
SCP, and the two SMC channels. The memory structures of the three SCC channels are
Table 2-6. System Configuration Register
Address
Name
Width
Description
Reset Value
$0F0
RES
16
Reserved
$0F2
*
BAR
16
Base Address Register
BFFF
$0F4
*
SCR
32
System Control Register
0000 0F00
$0F8
RES
16
Reserved
$0FA
CKCR
16
Clock Control Register
0000
$0FC
RES
32
Reserved
Table 2-7. System RAM
Address
Width
Block
Description
Base + 000
Base + 23F
576 Bytes
RAM
User Data Memory
Base +240
Base + 3FF
Reserved
(Not Implemented)


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