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LTC2268-12 Datasheet(PDF) 1 Page - Linear Technology |
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LTC2268-12 Datasheet(HTML) 1 Page - Linear Technology |
1 / 36 page Electrical Specifications Subject to Change 1 21421012p LTC2142-12/ LTC2141-12/LTC2140-12 TYPICAL APPLICATION FEATURES APPLICATIONS DESCRIPTION 12-Bit, 65Msps/ 40Msps/25Msps Low Power Dual ADCs n Communications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multi-Channel Data Acquisition n Nondestructive Testing n 2-Channel Simultaneously Sampling ADC n 70.8dB SNR n 89dB SFDR n Low Power: 92mW/65mW/48mW Total 46mW/33mW/24mW per Channel n Single 1.8V Supply n CMOS, DDR CMOS, or DDR LVDS Outputs n Selectable Input Ranges: 1VP-P to 2VP-P n 800MHz Full Power Bandwidth S/H n Optional Data Output Randomizer n Optional Clock Duty Cycle Stabilizer n Shutdown and Nap Modes n Serial SPI Port for Configuration n 64-Pin (9mm × 9mm) QFN Package The LTC ®2142-12/LTC2141-12/LTC2140-12 are 2-channel simultaneous sampling 12-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applica- tions with AC performance that includes 70.8dB SNR and 89dB spurious free dynamic range (SFDR). Ultralow jitter of 0.08psRMS allows undersampling of IF frequencies with excellent noise performance. DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature. The transition noise is 0.3LSBRMS. The digital outputs can be either full rate CMOS, double data rate CMOS, or double data rate LVDS. A separate output power supply allows the CMOS output swing to range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An optional clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 2-Tone FFT, fIN = 70MHz and 69MHz CMOS OR LVDS OUTPUTS 1.8V VDD 1.8V OVDD CLOCK CONTROL D1_11 D1_0 21421012 TA01a CH 1 ANALOG INPUT OUTPUT DRIVERS • • • GND OGND S/H 12-BIT ADC CORE CH 2 ANALOG INPUT S/H 12-BIT ADC CORE D2_11 D2_0 • • • 65MHz CLOCK FREQUENCY (MHz) –100 –110 –120 –70 –60 –80 –90 –50 –30 –40 –20 –10 0 21821012 TA01b FREQUENCY (MHz) 21821012 TA01b 0 10 20 30 |
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