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M68300 Datasheet(PDF) 89 Page - Motorola, Inc

Part # M68300
Description  QUad Integrated Communications Controller Users Manual
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Manufacturer  MOTOROLA [Motorola, Inc]
Direct Link  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

M68300 Datasheet(HTML) 89 Page - Motorola, Inc

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Bus Operation
MOTOROLA
MC68360 USER’S MANUAL
4-13
Figure 4-7. Word Operand Write Timing (8-Bit Data Port)
Figure 4-8 shows the transfer of a long-word operand to an odd address in word-organized
memory, which requires three bus cycles. For the first cycle, the SIZx signals specify a long-
word transfer, and the address offset (A2–A0) is 001. Since the port width is 16 bits, only the
first byte of the long word is transferred. The slave device latches the byte and acknowl-
edges the data transfer, indicating that the port is 16 bits wide. When the processor starts
the second cycle, the SIZx signals specify that three bytes remain to be transferred with an
address offset (A2–A0) of 010. The next two bytes are transferred during this cycle. The pro-
cessor then initiates the third cycle, with the SIZx signals indicating one byte remaining to
be transferred. The address offset (A2–A0) is now 100; the port latches the final byte, and
the operation is complete. Figure 4-9 shows the associated bus transfer signal timing.
BYTE WRITE
WORD OPERAND WRITE
S0
S2
S4
S0
S2
S4
CLKO1
A31–A2
A1
A0
FC3–FC0
SIZ1
SIZ0
R/W
AS
DS
DSACK1
DSACK0
D31–D24
D23–D16
BYTE WRITE
D15–D8
D7–D0
OP3
OP2
OP3
OP2
OP3
OP3
OP3
OP3


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