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MC68360 Datasheet(PDF) 79 Page - Motorola, Inc |
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MC68360 Datasheet(HTML) 79 Page - Motorola, Inc |
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79 / 962 page  Bus Operation MOTOROLA MC68360 USER’S MANUAL 4-3 4.1.1 Bus Control Signals The QUICC initiates a bus cycle by driving the address, size, function code, and read/write outputs. At the beginning of a bus cycle, SIZ1 and SIZ0 are driven with the FC signals. SIZ1 and SIZ0 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles). Table 4-3 lists the encoding of SIZ1 and SIZ0. These signals are valid while AS is asserted. The R/W signal determines the direction of the transfer during a bus cycle. Driven at the beginning of a bus cycle, R/W is valid while AS is asserted. R/W only transitions when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive write cycles. The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation. 4.1.2 Function Codes (FC3–FC0) The FCx signals are outputs that indicate one of 16 address spaces to which the address applies. Fifteen of these spaces are designated as either a normal or DMA cycle, user or supervisor, and program or data spaces. One other address space is designated as CPU space to allow the CPU32+ to acquire specific control information not normally associated with read or write bus cycles. The FCx signals are valid while AS is asserted. Function codes (see Table 4-1) can be considered as extensions of the 32-bit address that can provide up to eight different 4-Gbyte address spaces. Function codes are automatically generated by the CPU32+ to select address spaces for data and program at both user and supervisor privilege levels, and a CPU address space for processor functions. User pro- grams access only their own program and data areas to increase protection of system integ- rity and can be restricted from accessing other information. The S-bit in the CPU32+ status register is set for supervisor accesses and cleared for user accesses to provide differentia- tion. Refer to 4.4 CPU Space Cycles for more information. Table 4-1. Address Space Encoding Function Code Bits 3210 Address Spaces 0000 Reserved (Motorola) 0001 User Data Space 0010 User Program Space 0011 Reserved (User) 0100 Reserved (Motorola) 0101 Supervisor Data Space 0110 Supervisor Program Space 0111 Supervisor CPU Space 1 x x x DMA space |
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