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MC68360 Datasheet(PDF) 61 Page - Motorola, Inc |
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MC68360 Datasheet(HTML) 61 Page - Motorola, Inc |
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61 / 962 page  Signal Descriptions MOTOROLA MC68360 USER’S MANUAL 2-13 NOTE All CONFIG pins do have an internal pull-up resistor during re- set. If a configuration other than the default (CONFIG2-1 = 111) is desired, these pins should be driven by an active open collec- tor device during the assertion of RESETH. 2.1.14 Power Signals The following signals are used for power and ground to the QUICC. 2.1.14.1 VCCSYN AND GNDSYN. These pins provide power and ground to the clock syn- thesizer. They should be bypassed to each other with a 0.1- µF capacitor. See the system clock generation description in Section 6 System Integration Module (SIM60) for more details. 2.1.14.2 VCCCLK AND GNDCLK. These pins provide power and ground to the clock out- put pins (CLKO1 and CLKO2). They should be bypassed to each other with a 0.1- µF capac- itor. See the system clock generation description in Section 6 System Integration Module (SIM60) for more detail. 2.1.14.3 GNDS1 AND GNDS2. These two pins are special ground pins that, if used prop- erly, allow more aggressive timing to be provided on certain system bus pins. These pins include AS, CASx, and IPIPE. Section 10 Electrical Characteristics already shows the aggressive timing; the user does not need to modify any values in the section. GNDS1 and GNDS2 should be connected to a quiet ground source or to a low-noise ground plane. 2.1.14.4 VCC AND GND. These pins are the rest of the power and ground connections for the QUICC. 2.1.14.5 NC4–NC1. These four pins should not be connected on the QUICC package. They are reserved for future enhancements. Table 2-6. Initial Configuration Configuration Pins CONFIG2/ FREEZE CONFIG1/ BCLRO CONFIG0/ RMC Result 0 0 0 Slave mode; global CS 8-bit size; MBAR at $003FF00. 001 Slave mode; global CS 32-bit size; MBAR at $003FF00; not MC68040 com- panion mode; BR output, BG input. 0 1 0 Slave mode; global CS 16-bit size; MBAR at $003FF00. 011 MC68040 companion mode; global CS 32-bit size; MBAR at $003FF00; BR input, BG output. 1 0 0 CPU enabled; global CS 32-bit size; MBAR at $003FF00. 1 0 1 CPU enabled; global CS 16-bit size; MBAR at $003FF00. 1 1 0 Slave mode; global CS disabled; MBAR at $003FF04. 1 1 1 CPU enabled; global CS 8-bit size; MBAR at $003FF00. (Default) |
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