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DS31406

2-Input, 14-Output, Single DPLL Timing IC

with Sub-ps Output Jitter

General Description

The DS31406 is a flexible, high-performance timing IC

for diverse frequency conversion

and frequency

synthesis applications. On each of its two input clocks

and fourteen output clocks, the device can accept or

generate nearly any frequency between 2kHz and

750MHz.

The input clocks are divided down, fractionally scaled as

needed, and continuously monitored for activity and

frequency accuracy. The best input clock is selected,

manually or automatically, as the reference clock for the

rest of the device. A flexible, high-performance digital

PLL locks to the selected reference and provides

programmable bandwidth, very high resolution holdover

capability, and truly hitless switching between input

clocks. The digital PLL is followed by a clock synthesis

subsystem which has seven fully programmable digital

frequency synthesis blocks, three high-speed low-jitter

APLLs, and 14 output clocks, each with its own 32-bit

divider and phase adjustment. The APLLs provide

fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the DS31406 has all required

features and functions to serve as a central timing

function or as a line card timing IC. With a suitable

oscillator the DS31406 meets the requirements of

Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813,

and G.8262.

Applications

Frequency Conversion Applications in a Wide Variety of

Equipment Types

Telecom Line Cards or Timing Cards with Any Mix of

SONET/SDH, Synchronous Ethernet and/or OTN

Ports in WAN Equipment Including MSPPs, Ethernet

Switches, Routers, DSLAMs, and Base Stations

Ordering Information

PART

TEMP RANGE

PIN-PACKAGE

DS31406GN+

-40

C to +85C

256 CSBGA

+Denotes a lead(Pb)-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.

Features



Differential or CMOS/TTL Format



Any Frequency from 2kHz to 750MHz



Fractional Scaling for 64B/66B and FEC Scaling

(e.g., 64/66, 237/255, 238/255) or Any Other

Downscaling Requirement



Continuous Input Clock Quality Monitoring



Automatic or Manual Clock Selection



Two 2/4/8kHz Frame Sync Inputs



Hitless Reference Switching on Loss of Input



Automatic or Manual Phase Build-Out



Holdover on Loss of All Inputs



Programmable Bandwidth, 0.5mHz to 400Hz

 Produce Any 2kHz Multiple Up to 77.76MHz

 Per-DFS Clock Phase Adjust

 Output Frequencies to 750MHz

 High Resolution Fractional Scaling for FEC and

64B/66B (e.g., 255/237, 255/238, 66/64) or Any

Other Scaling Requirement

 Less than 1ps RMS Output Jitter

 Simultaneously Produce Three Low-Jitter Rates from

the Same Reference (e.g., 622.08MHz for SONET,

255/237*622.08MHz for OTU2, and 156.25MHz for

10GE)

 Nearly Any Frequency from <1Hz to 750MHz

 Each Group Slaves to a DFS Clock, Any APLL

Clock, or Any Input Clock (Divided and Scaled)

 Each Has a Differential Output (3 CML, 4 LVDS/

LVPECL

 32-Bit Frequency Divider Per Output

 Two Sync Pulse Outputs: 8kHz and 2kHz

 Suitable Line Card IC or Timing Card IC for

Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU

 Accepts and Produces Nearly Any Frequency Up

to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1,

NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M,

156.25M, and Nx19.44M Up to 622.08M

 Internal Compensation for Local Oscillator

Frequency Error

 SPI™ Processor Interface



1.8V Operation with 3.3V I/O (5V Tolerant)

19-5711; Rev 0; 12/10

ABRIDGED DATA SHEET