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DS31404 Datasheet(PDF) 2 Page - Maxim Integrated Products |
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DS31404 Datasheet(HTML) 2 Page - Maxim Integrated Products |
2 / 5 page DS31404 2 of 5 Application Example DPLL1 Path system timing from master and slave timing cards IC1 DS31404 DPLL2 Path IC2 19.44MHz, 38.88MHz, 25MHz, etc. line timing to master and slave timing cards 8kHz, 19.44MHz, 38.88MHz, 25MHz, etc. OC4 OC5 n recovered line clocks from SERDES SONET/SDH, 1GE, 10GE, OTN, FC etc. frequencies can be unrelated to one another 155.52M, 622.08M, 25M, 125M, 156.25M, etc. with or without fractional scaling for FEC, 64B/66B, etc. MANY other rates possible, including DS1, E1, DS3, E3, 10M and Nx19.44M. IC3, IC4 n 3 unrelated frequencies simultaneously at <1ps rms jitter plus other frequencies at somewhat higher jitter clock monitoring and selection, undo fractional scaling, frequency conversion clock monitoring and selection, hitless switching, holdover, frequency conversion, fractional scaling, jitter attenuation OC1, OC2 clocks to line card SERDES SONET/SDH, 1GE, 10GE, OTN, FC, etc. ABRIDGED DATA SHEET |
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