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MC68302FC16 Datasheet(PDF) 100 Page - Motorola, Inc |
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MC68302FC16 Datasheet(HTML) 100 Page - Motorola, Inc |
100 / 480 page System Integration Block (SIB) 3-50 MC68302 USER’S MANUAL MOTOROLA EXTAL can also accept a CMOS-level clock input. The crystal output (XTAL) connects the internal crystal generator output to an external crystal. If an external clock is used, XTAL should be left unconnected. The CLKO pin, which drives the high-speed system clock, may be used to synchronize other peripherals to the IMP system clock. 3.8 SYSTEM CONTROL The IMP system control consists of a System Control Register (SCR) that configures the fol- lowing functions: • System Status and Control Logic •AS Control During Read-Modify-Write-Cycles • Disable CPU (M68000) Logic • Bus Arbitration Logic with Low-Interrupt Latency Support • Hardware Watchdog • Low-Power (Standby) Modes • Freeze Control 3.8.1 System Control Register (SCR) The SCR is a 32-bit register that consists of system status and control bits, a bus arbiter con- trol bit, hardware watchdog control bits, low-power control bits, and freeze select bits. Refer to Figure 3-11, Table 3-7, and to the following paragraphs for a description of each bit in this register. The SCR is a memory-mapped read-write register. The address of this register is fixed at $0F4 in supervisor data space (FC = 5). Figure 3-11. System Control Register 31 30 29 28 27 26 25 24 0 0 0 0 IPA HWT WPV ADC 23 22 21 20 19 18 17 16 0 ERRE VGE WPVE RMCST EMWS ADCE BCLM 15 14 13 12 11 10 8 FRZW FRZ2 FRZ1 SAM HWDEN HWDCN2–HWDCN0 76 5 4 0 LPREC LPP16 LPEN LOW-POWER CLOCK DIVIDER |
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