 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS3170 Datasheet(PDF) 53 Page - Maxim Integrated Products |
|
||||||||||||||||||||||||||||||
DS3170 Datasheet(HTML) 53 Page - Maxim Integrated Products |
|
|
53 / 230 page  DS3170 DS3/E3 Single-Chip Transceiver 53 of 230 10 FUNCTIONAL DESCRIPTION 10.1 Processor Bus Interface 10.1.1 SPI Serial Port Mode The external processor bus can be configured to operate in SPI serial bus mode. See the section 8.3.4.1 for detailed timing diagrams. When SPI = 1, SPI bus mode is implemented using four signals: clock (CLK), master-out slave-in data (MOSI), master-in slave-out data (MISO), and chip select ( CS). Clock polarity and phase can be set by the D[7]/SPI_CPOL and D[6]/SPI_CPHA pins. The order of the address and data bits in the serial stream is selectable using the D[5]/SPI_SWAP pin. The R/W bit is always first and B bit is always last in the initial control word and are not effected by the D[5]/SPI_SWAP pin setting. 10.1.2 8/16 Bit Bus Widths The external processor bus can be sized for 8 or 16 bits using the WIDTH pin. When in 8-bit mode (WIDTH=0), the address is composed of all the address bits including A[0], the lower 8 data lines D[7:0] are used and the upper 8 data lines D[15:8] are not used and never driven during a read cycle. When in 16-bit mode (WIDTH=1), the address bus does not include A[0] (the LSB of the address bus is not routed to the chip) and all 16 data lines D[15:0] are used. See Figure 8-27 and Figure 8-29 for functional timing diagrams. 10.1.3 Ready Signal ( RDY) The RDY signal allows the microprocessor to use the minimum bus cycle period for maximum efficiency. When this signal goes low, the RD or WR cycle can be terminated. See Figure 8-35 for functional timing diagrams. Note: The RDY signal will not go active if the user attempts to read or write unused registers not assigned to any design blocks. The RDY signal will go active if the user writes or reads reserved registers or unused registers within design blocks. 10.1.4 Byte Swap Modes The processor interface can operate in byte swap mode when the data bus is configured for 16-bit operation. The A[0]/BSWAP pin is used to determine whether byte swapping is enabled. This pin should be static and not change while operating. When the A[0]/BSWAP pin is low the upper register bits REG[15:8] are mapped to the upper external data bus lines D[15:8], and the lower register bits REG[7:0] are mapped to the lower external data bus lines D[7:0]. When the A[0]/BSWAP pin is high the upper register bits REG[15:8] are mapped to the lower external data bus lines D[7:0], and the lower register bits REG[7:0] are mapped to the upper external data bus lines D[15:8]. See Figure 8-31 and Figure 8-32 for functional timing diagrams. 10.1.5 Read-Write/Data Strobe Modes The processor interface can operate in either read-write strobe mode or data strobe mode. When MODE=0 the read-write strobe mode is enabled and a negative pulse on RD performs a read cycle, and a negative pulse on WR performs a write cycle. When MODE=1 the data strobe mode is enabled and a negative pulse on DS when R/W is high performs a read cycle, and a negative pulse on DS when R/W is low performs a write cycle. The read-write strobe mode is commonly called the “Intel” mode, and the data strobe mode is commonly called the “Motorola” mode. 10.1.6 Clear on Read/Clear on Write Modes The latched status register bits can be programmed to clear on a read access or clear on a write access. The global control register bit GL.CR1.LSBCRE controls the mode that all of the latched registers are cleared. When LSBCRE=0, the latched register bits will be cleared when the register is written to and the write data has the register bits to clear set. When LSBCRE=1, the latched register bits that are set will be cleared when the register is read. |
Similar Part No. - DS3170_11 |
|
Similar Description - DS3170_11 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
