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DS3170 Datasheet(PDF) 42 Page - Maxim Integrated Products |
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DS3170 Datasheet(HTML) 42 Page - Maxim Integrated Products |
42 / 230 page DS3170 DS3/E3 Single-Chip Transceiver 42 of 230 Figure 8-13. DS3 Framed Mode Transmit Serial Interface Pin Timing TCLKO or TCLKI DS3 TSER DS3 TDEN TSOFO DS3 TGCLK TSOFI TSER DATA IS OVERWRITTEN WITH OH 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 Figure 8-14. E3 G.751 Framed Mode Transmit Serial Interface Pin Timing E3 TSER E3 TDEN E3 TGCLK TCLKO or TCLKI TSOFO TSOFI TSER DATA IS OVERWRITTEN WITH OH 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 Figure 8-15. E3 G.832 Framed Mode Transmit Serial Interface Pin Timing E3 TSER E3 TDEN E3 TGCLK TCLKO or TCLKI TSOFO TSER DATA IS OVERWRITTEN WITH OH TSOFI 6 7 8 9 10 11 12 13 1 2 3 4 5 14 15 16 17 18 19 20 8.3.3.2 DS3/E3 Framed Mode Receive Serial Interface Pin Functional Timing The RSER signal has the DS3 or E3 payload as well as the DS3 or E3 overhead bits. The RDEN signal is used to enable external logic for payload processing and will be high during the DS3 or E3 payload bits and low during the DS3 or E3 overhead bits. The RGCLK signal can also be used to clock only the DS3 or E3 payload bits into external logic since the clock is stopped during the DS3 or E3 overhead bits. The RSOFO signal marks the first overhead bit of the DS3 or E3 frame. Figure 8-16 to Figure 8-18 show the relationship between the receive serial interface pins. |
Similar Part No. - DS3170_11 |
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Similar Description - DS3170_11 |
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