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DS24B33S+T Datasheet(PDF) 3 Page - Maxim Integrated Products |
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DS24B33S+T Datasheet(HTML) 3 Page - Maxim Integrated Products |
3 / 22 page 4Kb 1-Wire EEPROM with 200k Write/Erase Cycles _______________________________________________________________________________________ 3 ELECTRICAL CHARACTERISTICS (continued) (TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN: 1-Wire WRITE Standard speed 60 120 Write-Zero Low Time (Notes 2, 16) tW0L Overdrive speed 6 16 μs Standard speed 5 15 Write-One Low Time (Notes 2, 16) tW1L Overdrive speed 1 2 μs IO PIN: 1-Wire READ Standard speed 5 15 - Read Low Time (Notes 2, 17) tRL Overdrive speed 1 2 - μs Standard speed tRL + 15 Read Sample Time (Notes 2, 17) tMSR Overdrive speed tRL + 2 μs EEPROM Programming Current IPROG (Note 18) 2 mA Programming Time tPROG (Note 19) 5 ms At +25°C 200,000 Write/Erase Cycles (Endurance) (Notes 20, 21) NCY At +85°C (worst case) 50,000 — Data Retention (Notes 22, 23, 24) tDR At +85°C (worst case) 40 Years Note 1: Not all parameters are tested at all temperatures. Note 2: System requirement. Note 3: When operating near the minimum operating voltage (2.8V), a falling edge slew rate of 15V/µs or faster is recommended. Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and current requirements during EEPROM programming. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00 or DS2480B may be required. Note 5: Capacitance on the data pin could be 2500pF when VPUP is first applied. If a 2.2k Ω resistor is used to pull up the data line, then 15µs after VPUP has been applied, the parasite capacitance does not affect normal communications. Note 6: Guaranteed by design, characterization, and/or simulation only. Not production tested. Note 7: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 8: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 9: The voltage on IO must be less than or equal to VILMAX at all times while the master is driving IO to a logic 0 level. Note 10: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 11: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0. Note 12: The I-V characteristic is linear for voltages less than +1V. Note 13: Applies to a single DS24B33 attached to a 1-Wire line. Note 14: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN). Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS24B33 present. Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN. Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively. Note 17: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF. Note 18: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO should be such that during the programming interval, the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, then a low-impedance bypass of RPUP, which can be activated during programming, may need to be added. Note 19: The tPROG interval begins after the trailing rising edge on IO for the last time slot of the E/S byte for a valid copy scratch- pad sequence. The interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL. |
Similar Part No. - DS24B33S+T |
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Similar Description - DS24B33S+T |
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