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R5F562T7EDFP Datasheet(PDF) 3 Page - Renesas Technology Corp |
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R5F562T7EDFP Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 94 page R01DS0096EJ0100 Rev.1.00 Page 3 of 92 Apr 20, 2011 RX62T Group 1. Overview Interrupt Interrupt control unit (ICU) Peripheral function interrupts: 101 sources External interrupts: 9 (NMI and IRQ0 to IRQ7 pins) Non-maskable interrupts: 3 (the NMI pin, oscillation stop detection interrupt, and voltage- monitoring interrupt) 16 levels specifiable for the order of priority Data transfer Data transfer controller (DTC) Three transfer modes: Normal transfer, repeat transfer, and block transfer Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral functions I/O ports Programmable I/O ports I/O port pins for devices in the 112-pin LQFP/100-pin LQFP/80-pin LQFP/64-pin LQFP I/O: 61/55/44/37 Input only: 21/21/13/9 Open-drain outputs: 2/2/2/2 (I2C bus interface pins) Large-current outputs: 12/12/6/6(0) (MTU3 and GPT pins) The 5-V version of the 64-pin product does not have large-current outputs. Reading out the states of pins is always possible. Timers Multi-function timer pulse unit 3 (MTU3) 16 bits x 8 channels Up to 24 pulse inputs/outputs and three pulse inputs Select from among six to eight counter-input clock signals for each channel (ICLK/1, ICLK/4, ICLK/16, ICLK/64, ICLK/256, ICLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than channel 5, for which only four signals are available. 24 output compare or input capture registers Counter clearing (clearing is synchronizable with compare match or input capture) Simultaneous writing to multiple timer counters (TCNT) Input to and output from all registers in synchronization with counter operation Buffered operation Cascade-connected operation 38 kinds of interrupt source Automatic transfer of register data Pulse output modes Toggled, PWM, complementary PWM, and reset synchronous PWM Complementary PWM output mode Outputs non-overlapping waveforms for controlling 3-phase inverters Automatic specification of dead times PWM duty cycle: Selectable as any value from 0% to 100% Delay can be applied to requests for A/D conversion. Non-generation of interrupt requests at peak or trough values of counters can be selected. Double buffering Reset-synchronous PWM mode Three PWM waveforms and corresponding inverse waveforms are output with the desired duty cycles. Phase-counting mode Counter functionality for dead-time compensation Generation of triggers for A/D converters Differential timing for initiation of A/D conversion Port output enable 3 (POE3) Control of the high-impedance state of the MTU3 and GPT’s waveform output pins 5 pins for input from signal sources: POE0, POE4, POE8, POE10, POE11 Initiation on detection of short-circuited outputs (detection of simultaneous switching of large-current pins to the active level) Initiation by comparator-detection of analog level input to the 12-bit A/D converter Initiation by oscillation-stoppage detection Initiation by software Selection of which output pins should be placed in the high-impedance state at the time of each POE input or comparator detection Table 1.1 Outline of Specifications (2 / 5) Classification Module/Function Description |
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