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R5F562TAADFM Datasheet(PDF) 4 Page - Renesas Technology Corp |
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R5F562TAADFM Datasheet(HTML) 4 Page - Renesas Technology Corp |
4 / 94 page R01DS0096EJ0100 Rev.1.00 Page 4 of 92 Apr 20, 2011 RX62T Group 1. Overview Timers General PWM timer (GPT) 16 bits x 4 channels Counting up or down (saw-wave), counting up and down (triangle-wave) selectable for all channels Clock sources independently selectable for all channels 2 input/output pins per channel 2 output compare/input capture registers per channel For the 2 output compare/input capture registers of each channel, 4 registers are provided as buffer registers and are capable of operating as comparison registers when buffering is not in use. In output compare operation, buffer switching can be at peaks or troughs, enabling the generation of laterally asymmetrically PWM waveforms. Registers for setting up frame intervals on each channel (with capability for generating interrupts on overflow or underflow) Synchronizable operation of the several counters Modes of synchronized operation (synchronized, or displaced by desired times for phase shifting) Generation of dead times in PWM operation Through combination of three counters, generation of automatic three-phase PWM waveforms incorporating dead times Starting, clearing, and stopping counters in response to external or internal triggers Internal trigger sources: output of the internal comparator detection, software, and compare-match The frequency-divided system clock (ICLK) can be used as a counter clock for measuring timing of the edges of signals produced by frequency-dividing the low-speed on-chip oscillator clock signal dedicated to IWDT (to detect abnormal oscillation). Compare match timer (CMT) (16 bits x 2 channels) x 2 units Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512) Watchdog timer (WDT) 8 bits x 1 channel Select from among eight counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768, PCLK/131072) Switchable between watchdog timer mode and interval timer mode Independent watchdog timer (IWDT) 14 bits x 1 channel Counter-input clock: low-speed on-chip oscillator dedicated to IWDT Communications Serial communications interface (SCIb) 3 channels Serial communications modes: Asynchronous, clock synchronous, and smart-card interface Multiprocessor communications On-chip baud rate generator allows selection of the desired bit rate Choice of LSB-first or MSB-first transfer Noise cancellation (only available in asynchronous mode) I2C bus interface (RIIC) 1 channel Communications formats I2C bus format/SMBus format Master/slave selectable Table 1.1 Outline of Specifications (3 / 5) Classification Module/Function Description |
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