 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MC68302PV16 Datasheet(PDF) 72 Page - Motorola, Inc |
|
||||||||||||||||||||||||||||||
MC68302PV16 Datasheet(HTML) 72 Page - Motorola, Inc |
|
|
72 / 480 page  System Integration Block (SIB) 3-22 MC68302 USER’S MANUAL MOTOROLA Option 2. The external peripheral can generate the vector. In this case the external device must decode the interrupt acknowledge cycle, put out the 8-bit vector, and generate DTACK. The decoding of the interrupt acknowledge cycle can be provided by the IACK7, IACK6, and IACK1 signals (enabled in the PBCNT register) if either normal or dedicated mode is cho- sen. These signals eliminate the need for external logic to perform the decoding of the A19– A16, A3–A1, and FC2–FC0 pins externally to detect the interrupt acknowledge cycle. If the IACK signals are not needed, they can be regained as general purpose parallel I/O pins. The external device must generate DTACK in this mode, and DTACK is an input to the IMP. Option 3. The external peripheral can assert the AVEC pin to cause the M68000 to use an autovector. In this case, DTACK should not be asserted by the external device. AVEC is rec- ognized by the M68000 core on the falling edge of S4 and should meet the asynchronous setup time to the falling edge of S4. The IACK signals can be used to help generate the AVEC signal for priority levels 1, 6, and 7, if needed. NOTE If AVEC is asserted during an interrupt acknowledge cycle, an autovector is taken, regardless of the vector on the bus. AVEC should not be asserted during level 4 interrupt acknowledge cy- cles. When the IMP generates the vector, the following procedure is used. The three most signif- icant bits of the interrupt vector number are programmed by the user in the GIMR. These three bits are concatenated with five bits generated by the interrupt controller to provide an 8-bit vector number to the core. The interrupt controller's encoding of the five low-order bits of the interrupt vector is shown in Table 3-5. An example vector calculation is shown in Fig- ure 3-4. When the core initiates an interrupt acknowledge cycle for level 4 and there is no internal interrupt pending, the interrupt controller encodes the error code 00000 onto the five low-order bits of the interrupt vector. |
Similar Part No. - MC68302PV16 |
|
Similar Description - MC68302PV16 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
