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MC68302PV16 Datasheet(PDF) 65 Page - Motorola, Inc |
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MC68302PV16 Datasheet(HTML) 65 Page - Motorola, Inc |
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65 / 480 page  System Integration Block (SIB) MOTOROLA MC68302 USER’S MANUAL 3-15 3.1.7.1 Reset Upon an external chip reset, the IDMA channel immediately aborts the channel operation, returns to the idle state, and clears CSR and CMR (including the STR bit). If a bus cycle is in progress when reset is detected, the cycle is terminated, the control and address/data pins are three-stated, and bus ownership is released. The IDMA can also be reset by RST in the CMR. 3.1.7.2 Bus Error When a fatal error occurs during a bus cycle, a bus error exception is used to abort the cycle and systematically terminate that channel's operation. The IDMA terminates the current bus cycle, signals an error in the CSR, and generates a maskable interrupt. The IDMA clears STR and waits for a restart of the channel and the negation of BERR before starting any new bus cycles. NOTE Any data that was previously read from the source into the DHR will be lost. 3.1.7.3 Halt IDMA transfer operation may be suspended at any time by asserting HALT to the IDMA. In response, any bus cycle in progress is completed (after DTACK is asserted), and bus own- ership is released. No further bus cycles will be started while HALT remains asserted. When the IDMA is in the middle of an operand transfer when halted and HALT is subsequently ne- gated, and if a new transfer request is pending, then IDMA will arbitrate for the bus and con- tinue normal operation. 3.1.7.4 Relinquish and Retry When HALT and BERR are asserted during a bus cycle, the IDMA terminates the bus cycle, releases the bus, and suspends any further operation until these signals are negated. When HALT and BERR are negated, the IDMA will arbitrate for the bus, re-execute the interrupted bus cycle, and continue normal operation. 3.2 INTERRUPT CONTROLLER The IMP interrupt controller accepts and prioritizes both internal and external interrupt re- quests and generates a vector number during the CPU interrupt acknowledge cycle. Inter- rupt nesting is also provided so that an interrupt service routine of a lower priority interrupt may be suspended by a higher priority interrupt request. The interrupt controller block dia- gram is shown in Figure 3-2. The on-chip interrupt controller has the following features: • Two Operational Modes: Normal and Dedicated • Eighteen Prioritized Interrupt Sources (Internal and External) • A Fully Nested Interrupt Environment • Unique Vector Number for Each Internal/External Source Generated • Three Interrupt Request and Interrupt Acknowledge Pairs |
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