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MC68302PV16 Datasheet(PDF) 62 Page - Motorola, Inc |
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MC68302PV16 Datasheet(HTML) 62 Page - Motorola, Inc |
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62 / 480 page  System Integration Block (SIB) 3-12 MC68302 USER’S MANUAL MOTOROLA DREQ input to the IDMA is level-sensitive and is sampled at certain points to determine when a valid request is asserted by the device. The device requests service by asserting DREQ and leaving it asserted. In response, the IDMA arbitrates for the system bus and begins to perform an operand transfer. During each access to the device, the IDMA will assert DACK to indicate to the device that a request is being serviced. If DREQ remains asserted when the IDMA completes the peripheral cycle (the cycle during which DACK is asserted by the IDMA) one setup time (see specification. 80) before the S5 falling edge (i.e., before or with DTACK), then a valid request for another operand transfer is recog- nized, and the IDMA will service the next request immediately. If DREQ is negated one setup time (see specification 80) before the S5 falling edge, a new request will not be rec- ognized, and the IDMA will relinquish the bus. NOTE: If 8 to 16 bit packing occurs, then the DREQ is sampled during the last 8-bit cycle. External Cycle Steal For external devices that generate a pulsed signal for each operand to be transferred, the external cycle steal mode uses DREQ as a falling edge-sensitive input. The IDMA will re- spond to cycle-steal requests in the same manner as for all other requests. However, if subsequent DREQ pulses are generated before DACK is asserted in response to each request, they will be ignored. If DREQ is asserted after the IDMA asserts DACK for the previous request but one setup time (see specification 80) before the S5 falling edge, then the new request will be serviced before the bus is relinquished. If a new request has not been generated by one setup time (see specification 80) before the S5 falling edge, the bus will be released to the next bus master. 3.1.4.5 Block Transfer Termination The user may stop the channel by clearing STR. Additionally, the channel operation can be terminated for any of the following reasons: transfer count exhausted, external device termi- nation, or error termination. This is independent of how requests are generated to the IDMA. Transfer Count Exhausted When the channel begins an operand transfer, if the current value of the BCR is one or two (according to the operand size in the CMR), DONE is asserted during the last bus cy- cle to the device to indicate that the channel operation will be terminated when the current operand transfer has successfully completed. In the memory to memory case, DONE is asserted during the last access to memory (source or destination) as defined by the ECO bit. When the operand transfer has completed and the BCR has been decremented to ze- ro, the channel operation is terminated, STR is cleared, and an interrupt is generated if INTN is set. The SAPR and/or DAPR are also incremented in the normal fashion. NOTE If the channel is started with BCR value set to zero, the channel will transfer 64K bytes. |
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