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MC68302 Datasheet(PDF) 28 Page - Motorola, Inc |
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MC68302 Datasheet(HTML) 28 Page - Motorola, Inc |
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28 / 480 page  General Description 1-6 MC68302 USER’S MANUAL MOTOROLA In the example shown in Figure 1-4, one SCC channel connects through the NMSI mode to a commercial packet data network. This connection might be used for remote status moni- toring or for maintenance functions for a system. Another SCC is used to connect to a local asynchronous terminal. The other SCC channel is used as a local synchronous channel, which could connect to another computer or subsystem. The SCP channel could then be used for local interconnection of interface chips or peripherals to the MC68302-based sys- tem. 1.5 BASIC RATE ISDN OR DIGITAL VOICE/DATA TERMINAL A basic rate ISDN (2B + D) or digital voice/data terminal can be made from a chip set based on the MC68302. Refer to Figure 1-5 for an example of a basic rate ISDN voice/data termi- nal. In this terminal, the CP can directly support the 2B + D channels and perform either V.110 or V.120 rate adaption. The physical layer serial interface is connected to the local interconnection bus (IDL in Figure 1-5, but the GCI and PCM buses can also be supported). The system then supports one of the B channels for voice (connected directly to the physical bus). The D channel consists of one SCC port; the other B channel is used for data transfer through a second SCC port. The data can be routed to a terminal (RS-232 type) via the third SCC port in the NMSI mode. The SCP functions as a control channel for the IDL bus in this case. Some ISDN physical layer devices support the signaling and framing functions of the D channel. In these cases, the D channel can connect through the microprocessor interface to the physical layer device, and the extra SCC port can then be used for a second B channel to transfer data. The benefit of a local interconnection bus (see Figure 1-5) versus a microprocessor bus is a lower pin count. It is also easy to maintain this low pin-count interface between several different interface chips, such as the MC145554 PCM codec/filter monocircuit and the MC145474 S/T transceiver. The MC68302 combines the M68000 architecture with a number of peripherals for integrat- ed applications in communications control. The M68000 core manages the CP through the on-chip, dual-port RAM and internal registers. The base address of the dual-port RAM and internal registers is selected through the base address register. Other peripherals are also accessed and controlled through internal registers: the IDMA controller, the three timers, I/O ports, and the interrupt controller. |
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