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MC68302 Datasheet(PDF) 71 Page - Motorola, Inc |
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MC68302 Datasheet(HTML) 71 Page - Motorola, Inc |
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71 / 480 page  System Integration Block (SIB) MOTOROLA MC68302 USER’S MANUAL 3-21 Figure 3-3. Interrupt Request Logic Diagram for SCCs 3.2.4 Interrupt Vector Pending EXRQ interrupts and unmasked INRQ interrupts are presented to the M68000 core in order of priority. The M68000 core responds to an interrupt request by initiating an inter- rupt acknowledge cycle to receive a vector number, which allows the core to locate the in- terrupt's service routine. If an INRQ source generated the interrupt, the interrupt controller always provides the vector corresponding to the highest priority, unmasked, pending interrupt. If an EXRQ source gen- erated the interrupt, three options are available to generate the vector. Option 1. By programming the GIMR, the user can enable the interrupt controller to provide the vector for any combination of EXRQ interrupt levels 1, 6, and 7. This is available regard- less of whether normal or dedicated mode is selected. Whenever a vector is provided by the interrupt controller, DTACK is also provided by the interrupt controller during that interrupt acknowledge cycle. DTACK is an output from the IMP in this case. The IMP can generate vectors for up to seven external peripherals by connecting the exter- nal request lines to IRQ7, IRQ6, IRQ1, PB11, PB10, PB9, and PB8. PB11, PB10, PB9, and PB8 are prioritized within level 4. SCCM IMR IPR INTERRUPT PRIORITY RESOLVER INTERNAL IPL2–IPL0 TO THE M68000 CORE 16-INPUT OR SCCE EVENT BIT MASK BIT 8-INPUT OR |
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