2

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FSB50250UD Rev. A

Pin Descriptions

Note:

ure 2 and 5.

Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)

Pin Number

Pin Name

Pin Description

1

COM

IC Common Supply Ground

2

Bias Voltage for U Phase High Side FRFET Driving

3

Bias Voltage for U Phase IC and Low Side FRFET Driving

4

Signal Input for U Phase High-side

5

Signal Input for U Phase Low-side

6

Bias Voltage Ground for U Phase High Side FRFET Driving

7

Bias Voltage for V Phase High Side FRFET Driving

8

Bias Voltage for V Phase IC and Low Side FRFET Driving

9

Signal Input for V Phase High-side

10

Signal Input for V Phase Low-side

11

Bias Voltage Ground for V Phase High Side FRFET Driving

12

Bias Voltage for W Phase High Side FRFET Driving

13

Bias Voltage for W Phase IC and Low Side FRFET Driving

14

Signal Input for W Phase High-side

15

Signal Input for W Phase Low-side

16

Bias Voltage Ground for W Phase High Side FRFET Driving

17

P

Positive DC–Link Input

18

U

Output for U Phase

19

Negative DC–Link Input for U Phase

20

Negative DC–Link Input for V Phase

21

V

Output for V Phase

22

Negative DC–Link Input for W Phase

23

W

Output for W Phase

COM

VCC

LIN

HIN

VB

HO

VS

LO

COM

VCC

LIN

HIN

VB

HO

VS

LO

COM

VCC

LIN

HIN

VB

HO

VS

LO

(1) COM

(17) P

(18) U

(21) V

(23) W