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PX1011B-N Datasheet(PDF) 9 Page - NXP Semiconductors |
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PX1011B-N Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 32 page  PX1011B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 18 April 2011 9 of 32 NXP Semiconductors PX1011B PCI Express stand-alone X1 PHY The de-serializer or Serial-to-Parallel converter (S2P) de-serializes this data into 10-bits parallel data. Since the S2P has no knowledge about the data, the word alignment is still random. This is fixed in the digital domain by the PCS block. It first detects a 10-bit comma character (K28.5) from the random data stream and aligns the bits. Then it converts the 10-bit raw data into 8-bit words using 8b/10b decoding. An elastic buffer and FIFO brings the resulting data to the right clock domain, which is the RX source synchronous clock domain. 8.2 Transmitting data When the PHY transmits, it receives 8-bit data from the MAC. This data is encoded using an 8b/10b encoding algorithm. The 2 bits overhead of the 8b/10b encoding ensures the serial data will be DC-balanced and has a sufficient 0-to-1 and 1-to-0 transition density for clock recovery at the receiver side. The serializer or Parallel-to-Serial converter (P2S) serializes the 10 bits data into serial data streams. These data streams are latched into the transmitter, where they are converted into small amplitude differential signals. The transmitter has built-in de-emphasis for a larger eye opening at the receiver side. The PLL has a sufficiently high bandwidth to handle a 100 MHz reference clock with a 30 kHz to 33 kHz spread spectrum. 8.3 Clocking There are three clock signals used by the PX1011B: • REFCLK is a 100 MHz external reference clock that the PHY uses to generate the 250 MHz data clock and the internal bit rate clock. This clock may have 30 kHz to 33 kHz spread spectrum modulation. • TXCLK is a reference clock that the PHY uses to clock the TXDATA and command. This source synchronous clock is provided by the MAC. The PHY expects that the rising edge of TXCLK is centered to the data. The TXCLK has to be synchronous with RXCLK. • RXCLK is a source synchronous clock provided by the PHY. The RXDATA and status signals are synchronous to this clock. The PHY aligns the rising edge of RXCLK to the center of the data. RXCLK may be used by the MAC to clock its internal logic. 8.4 Reset The PHY must be held in reset until power and REFCLK are stable. It takes the PHY 64 μs maximum to stabilize its internal clocks. RXCLK frequency is the same as REFCLK frequency, 100 MHz, during this time. The PHY de-asserts PHYSTATUS when internal clocks are stable. The PIPE specification recommends that while RESET_N is asserted, the MAC should have RXDET_LOOPB de-asserted, TXIDLE asserted, TXCOMP de-asserted, RXPOL de-asserted and power state P1. The MAC can also assert a reset if it receives a physical layer reset packet. |
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