© 2008 Fairchild Semiconductor Corporation

www.fairchildsemi.com

SG6741 • Rev. 1.3.3

3

Marking Information

T: S = SOP

P: Z =Lead Free

Null=regular package

XXXXXXXX: Wafer Lot

Y: Year; WW: Week

V: Assembly Location

F: Fairchild logo

Z: Plant code

X: 1 digit year code

Y: 1 digit week code

TT: 2 digits die run code

T: Package type (S = SOP)

P: Y=Green package

M: Manufacture flow code

SG6741TP

XXXXXXXXYWWV

ZXYTT

6741

TPM

Marking for SG6741SZ

Marking for SG6741SY

Figure 3. Top Mark

Pin Configuration

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin #

Name

Description

1

GND

Ground.

2

FB

The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is

determined in response to the signal on this pin and the current-sense signal on the SENSE pin.

3

NC

No connection.

4

HV

For startup, this pin is pulled high to the line input or bulk capacitor via resistors.

5

RI

A resistor connected from the RI pin to GND pin provides the SG6741 with a constant current

source. This determines the center PWM frequency. Increasing the resistance reduces PWM

6

SENSE

Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle

current limiting.

7

VDD

OVP trigger point.

8

GATE

The totem-pole output driver. Soft driving waveform is implemented for improved EMI.

GATE

VDD

SENSE

RI

GND

FB

NC

HV