© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FSQ510, FSQ510H, and FSQ510M • Rev. 1.3.0

3

Pin Assignments

GND

Sync

FSQ510H

D

GND

GND

Figure 3.

Package Diagrams for FSQ510(M) and FSQ510H

Pin Definitions

7-Pin

8-Pin

Name

Description

1, 2

4, 5, 6

GND

This pin is the control ground and the SenseFET source.

3

2

This pin is internally connected to the inverting input of the PWM

comparator. The collector of an opto-coupler is typically tied to this

pin. For stable operation, a capacitor should be placed between this

pin and GND. If the voltage of this pin reaches 4.7V, the overload

protection triggers, which shuts down the FPS.

4

3

Sync

This pin is internally connected to the sync-detect comparator for

valley switching. In normal valley-switching operation, the threshold of

the sync comparator is 0.7V/0.1V.

5

7

This pin is the positive supply input. This pin provides internal

operating current for both startup and steady-state operation.

7

8

D

High-voltage power SenseFET drain connection.

8

1

This pin is connected directly, or through a resistor, to the high-

voltage DC link. At startup, the internal high-voltage current source

supplies internal bias and charges the external capacitor connected

disabled.