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FSQ510 Datasheet(PDF) 9 Page - Fairchild Semiconductor

Part # FSQ510
Description  Green Mode Fairchild Power Switch
Download  15 Pages
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FSQ510 Datasheet(HTML) 9 Page - Fairchild Semiconductor

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© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSQ510, FSQ510H, and FSQ510M • Rev. 1.3.0
9
Functional Description
1. Startup:
At startup, an internal high-voltage current
source supplies the internal bias and charges the
external capacitor (Ca) connected to the VCC pin, as
illustrated in Figure 13. When VCC reaches 8.7V, the
FPS begins switching and the internal high-voltage
current source is disabled. The FPS continues normal
switching operation and the power is supplied from the
auxiliary transformer winding unless VCC goes below the
stop voltage of 6.7V.
6.7V/
8.7V
5
V
ref
Internal
Bias
V
CC
8
V
str
I
CH
V
CC good
V
DC
C
a
Figure 13. Startup Block
2. Feedback Control
: This device employs current-
mode control, as shown in Figure 14. An opto-coupler
(such as the FOD817) and shunt regulator (such as the
KA431) are typically used to implement the feedback
network. Comparing the feedback voltage with the
voltage across the Rsense resistor makes it possible to
control the switching duty cycle. When the reference pin
voltage of the shunt regulator exceeds the internal
reference voltage of 2.5V, the opto-coupler LED current
increases, pulling down the feedback voltage and
reducing the drain current. This typically occurs when the
input voltage is increased or the output load is decreased.
2.1 Pulse-by-Pulse Current Limit
: Because current-
mode control is employed, the peak current through the
SenseFET is limited by the inverting input of PWM
comparator (VFB*), as shown in Figure 14. Assuming
that the 225µA current source flows only through the
internal resistor (6R + R=12.6k
Ω), the cathode voltage
of diode D2 is about 2.8V. Since D1 is blocked when
the feedback voltage (VFB) exceeds 2.8V, the maximum
voltage of the cathode of D2 is clamped at this voltage,
clamping VFB*. Therefore, the peak value of the current
through the SenseFET is limited.
2.2 Leading-Edge Blanking (LEB)
: At the instant the
internal SenseFET is turned on, a high-current spike
usually occurs through the SenseFET, caused by
primary-side capacitance and secondary-side rectifier
reverse recovery. Excessive voltage across the Rsense
resistor would lead to incorrect feedback operation in
the current mode VS-PWM control. To counter this
effect, the FPS employs a leading-edge blanking
(LEB) circuit to inhibit the VS-PWM comparator for a
short time (tLEB) after the SenseFET is turned on.
OSC
V
ref
I
delay
I
FB
VSD
R
6R
Gate
driver
OLP
D1
D2
+
V
fb
*
-
V
fb
KA431
OB
V
O
FOD817
R
sense
SenseFET
V
ref
VS signal
3
Figure 14. Valley Switching Pulse-Width
Modulation (VS-PWM) Circuit
3. Synchronization
: The FSQ510 (H or M) employs a
valley-switching technique to minimize the switching
noise and loss. The basic waveforms of the valley
switching converter are shown in Figure 15. To
minimize the MOSFET switching loss, the MOSFET
should be turned on when the drain voltage reaches its
minimum value, as shown in Figure 15. The minimum
drain voltage is indirectly detected by monitoring the
V
B
CC
B
winding voltage, as shown in Figure 15.
V
DC
V
RO
V
RO
V
DS
t
F
0.7V
V
Sync
200ns Delay
0.1V
MOSFET
Gate
ON
ON
Figure 15. Valley Switching Waveforms


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