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FAN48002S Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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FAN48002S Datasheet(HTML) 10 Page - Fairchild Semiconductor |
10 / 19 page © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN4800AS/CS/01S/02S • Rev. 1.0.1 10 Electrical Characteristics (Continued) Unless otherwise noted, VDD=15V, TA= 25°C, TA=TJ, RT=6.8kΩ, and CT=1000pF. Symbol Parameter Conditions Min. Typ. Max. Unit PFC Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 13 15 17 V VGATE-L Gate Low Voltage VDD=15V, IO = 100mA 1.5 V VGATE-H Gate High Voltage VDD=13V, IO = 100mA 8 V tR Gate Rising Time VDD=15V, CL=4.7nF, O/P= 2V to 9V 40 70 120 ns tF Gate Falling Time VDD=15V; CL=4.7nF, O/P= 9V to 2V 40 60 110 ns DPFC-MAX Maximum Duty Cycle VIEA<1.2V 94 97 % DPFC-MIN Minimum Duty Cycle VIEA>4.5V 0 % Brownout VRMS-UVL VRMS Threshold Low When VRMS=1.05V at 75VRMS 1.03 1.05 1.08 V VRMS-UVH VRMS Threshold High When VRMS=1.9V at 85•1.414 1.88 1.90 1.94 V VRMS-UVP Hysteresis 750 850 950 mV tUVP Under Voltage Protection Debounce Time 850 1000 1150 ms Soft Start VSS-MAX Maximum Voltage VDD=15V 9.5 10.0 10.5 V ISS Soft-Start Current 10 µA PWM ILIMIT Comparator VPWM-ILIMIT Threshold Voltage 0.95 1.00 1.05 V tPD Propagation Delay to Output 250 ns tPWM-BNK Leading-Edge Blanking Time 170 250 350 ns Range (FAN4801S/02S) VVRMS-L RMS AC Voltage Low When VVRMS =1.95V at 132VRMS 1.90 1.95 2.00 V VVRMS-H RMS AC Voltage High When VVRMS =2.45V at 150VRMS 2.40 2.45 2.50 V VVEA-L VEA LOW When VVEA= 1.95V at 30% Loading 1.90 1.95 2.00 V VVEA-H VEA HIGH When VVEA= 2.45V at 40% Loading 2.40 2.45 2.50 V ITC Source Current from FBPFC 18 20 22 µA PWM Output Driver VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 18 19 20 V VGATE-L Gate Low Voltage VDD=15V, IO=100mA 1.5 V VGATE-H Gate High Voltage VDD=13V, IO=100mA 8 V tR Gate Rising Time VDD=15V, CL=4.7nF 30 60 120 ns tF Gate Falling Time VDD=15V, CL=4.7nF 30 50 110 ns DPWM-MAX Maximum Duty Cycle 49.0 49.5 50.0 % VPWM-LS PWM Comparator Level Shift 1.3 1.5 1.8 V Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. This GAIN is the maximum gain of modulation with a given VRMS voltage when VVEA is saturated to HIGH. |
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