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FFPF10H60S Datasheet(PDF) 9 Page - Fairchild Semiconductor

Part # FFPF10H60S
Description  Power Factor Correction Converter Design
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FFPF10H60S Datasheet(HTML) 9 Page - Fairchild Semiconductor

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AN-6982
APPLICATION NOTE
© 2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 6/8/10
9
,
(1 cos(4
))
D AVG
BOUT
LINE
I
If
t
π
=−
BOUT
I
,
2
BOUT
BOUT RIPPLE
LINE BOUT
I
V
fC
π
=
BOUT
V
,
DAVG
I
D
I
Figure 16. PFC Output Voltage Ripple
(Design Example)
With the ripple specification of
12VPP, the capacitor should be:
,
0.9
239
22
50 12
BOUT
BOUT
LINE
BOUT RIPPLE
I
CF
fV
μ
ππ
>=
=
⋅⋅
Since minimum allowable output voltage during one
cycle line (20ms) drop-outs is 310V, the capacitor
should be:
3
22
2
2
,
2
2 349 20 10
260
387
310
BOUT
HOLD
BOUT
OUT
OUT MIN
Pt
CF
VV
μ
⋅⋅
×
>=
=
−−
Thus, 270
μF capacitor is selected for the PFC output
capacitor.
[STEP-5] PFC Output Sensing Circuit
To improve system efficiency at low-line and light-load
condition, FAN6982 provides two-level PFC output
voltage. As shown in Figure 17, the range function can be
enabled or disabled through a resistor connected to ground
or VREF. FAN6982 monitors VEA and VRMS voltages to
adjust the PFC output voltage and enables a 20µA current
source.
The PFC output voltage when 20µA is enabled is given as:
2
2
20
(1
)
2.5
FB
BOUT
BOUT
μAR
VV
-
×
(23)
It is typical to set the second boost output voltage as
340V~300V. It should be checked if the output voltage is
higher than the peak of the line voltage
12
3
2
3
2.45
2
RMS
RMS
RMS
BOUT
RMS
RR
R
V
R
π
++
⋅⋅
<
(24)
Figure 17. Block of Range Function
The voltage divider network for the PFC output voltage
sensing should be designed such that FBPFC voltage is
2.5V at nominal PFC output voltage:
2
12
2.5
FB
BOUT
FB
FB
R
VV
RR
×=
+
(25)
(Design Example)
Assuming the second level of
PFC output voltage is 347V:
2
2
6
6
2.5
(1
)
20 10
347
2.5
(1
)
12.9
387 20 10
BOUT
FB
BOUT
V
R
V
k
=−
×
= −⋅
=
Ω
×
13k
Ω is selected for RFB2.
It is checked if the output voltage is higher than the
peak of the line voltage:
12
3
3
63
3
3
2.45
2
2 10
200 10
36 10
2.45
2
36 10
239
347
RMS
RMS
RMS
RMS
RR
R
R
VV
π
π
++
⋅⋅
×+
×
+
×
=⋅ ⋅
×
=<
Then, to obtain 387V for nominal PFC output,
12
3
(1)
2.5
387
(1) 13 10
1999
2.5
BOUT
FB
FB
V
RR
k
=− ⋅
=
−⋅ ×
=
Ω
2M
Ω is selected for RFB1.
2.5V
+
-
VDD
RFB1
RFB2
FBPFC
20µA
1.95/2.45
VEA
VRMS
+
-
1.95/2.45
VREF
EN
+
-
3.75
SGND
VBOUT


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