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AN-6961 Datasheet(PDF) 3 Page - Fairchild Semiconductor

Part # AN-6961
Description  Critical Conduction Mode PFC Controller
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

AN-6961 Datasheet(HTML) 3 Page - Fairchild Semiconductor

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AN-6961
APPLICATION NOTE
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.2 • 4/8/09
3
Block Operation Description
Multi-Vector Error Amplifier
The FAN6961 has a trans-conductance type amplifier that
provides better dynamic performance. Referring to Figure 6,
the error amplifier output VEA is compared with a sawtooth
waveform to generate a fixed on-time. To achieve a low
input current THD, the variation of the on-time within one
input AC cycle should be very small. Therefore, the
bandwidth of the feedback loop should be set below 20Hz
to maintain a constant on-time for a line half-cycle.
Connecting a capacitance CEA, such as 1µF, between
COMP and GND is suggested.
t
_
EA out
V
PWM
Gate
ds
V
()
L
it
t
t
t
()
g
b
Vt
L
-( )
og
b
VV t
L
on
t
Sawtooth Generator
()
g
Vt
off
t
Figure 6. Operation Waveforms of Fixed On Time
Technique
For fast transient response and precise clamping of the
output voltage overshoot and undershoot, the FAN6961 has
a built-in multi-vector error amplifier. Figure 7 shows the
block diagram of the multi-vector error amplifier. When the
variation of the feedback voltage exceeds +6% and -8% of
the reference voltage, the multi-vector error amplifier
adjusts its output impedance to increase the loop response.
1
2
FAN6961
2.65V
2.3V
INV
CO
VO
Vref(2.5V)
VEA_OUT
CEA
COMP
Error
Amplifier
Figure 7. Block Diagram of the Multi-Vector Error
Amplifier
Total Harmonic Distortion (THD) Optimization
As discusses previously, the FAN6961 uses the controlled
on-time technique to achieve power factor correction
mechanism. However, to get better THD at light load
condition, especially at high input voltage, a THD
optimization circuit is inserted into the FAN6961. With this
internal THD optimization circuit, the on-time of the power
MOSFET is modulated to further improve the THD
performance. The calculated on-time variation within one
line voltage period with the fixed on-time technique, and
after the THD optimization is added, are shown in Figure 8.
The calculated input current waveform is shown in Figure 9.
5.00E-07
2.50E-06
4.50E-06
6.50E-06
8.50E-06
1.05E-05
1.25E-05
1.45E-05
1.65E-05
1.85E-05
0
20
40
60
80
100
120
140
160
Time(S/10000)
THD Optimization(Vac=90V,Vo=250V)
Fixed On Time(Vac=90V,Vo=250V)
THD Optimization(Vac=264V,Vo=400V)
Fixed On Time(Vac=264V,Vo=400V)
Figure 8. MOS Turn-on Time Calculational Curve
(Before and After THD Optimization Circuit Added)
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0
20
40
60
80
100
120
140
160
Time(S/10000)
THD Optimization(Vac=90V,Vo=250V)
Fixed On Time(Vac=90V,Vo=250V)
THD Optimization(Vac=264V,Vo=400V)
Fixed On Time(Vac=264V,Vo=400V)
Figure 9. Calculated Waveforms of the Input Current
(Before and After THD Optimization Circuit Added)


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