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KS8695P Datasheet(PDF) 30 Page - Micrel Semiconductor |
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KS8695P Datasheet(HTML) 30 Page - Micrel Semiconductor |
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30 / 42 page  Micrel, Inc. KS8695P May 2006 30 M9999-051806 General Purpose I/O Pins (continued) Pin Name I/O Type (1) Description D1 PCLKOUT3 O PCI clock output 3. In host bridge mode driven as 33MHz In guest bridge mode, this signal is reserved C1 PCLKOUT2 O PCI clock output 2. In host bridge mode driven as 33MHz In guest bridge mode, this signal is reserved B1 PCLKOUT1 O PCI clock output 1. In host bridge mode driven as 33MHz In guest bridge mode, this signal is reserved A2 PCLKOUT0 O PCI clock output 0. In host bridge mode driven as 33MHz In guest bridge mode, this signal is reserved B10 CLKRUNN I/O This is a cardbus only signal. The CLKRUNN signal is used by portable cardbus devices to request that the system turn on the bus clock. Output is always active in cardbus and miniPCI modes. D2 MPCIACTN O MiniPCI active. This signal is asserted by the PCI device to indicate that its current function requires full system performance. MPCIACTN is an open drain output signal. In miniPCI mode, this signal is always low. D3 PBMS I PCI bridge mode select. This selects the operating mode for the PCI bridge. When PBMS is high, the host bridge mode is selected and the on-chip PCI bus arbiter is enabled. When PBMS is low, the guest bridge mode is selected and the on-chip arbiter is disabled. Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O) Pin Name I/O Type (1) Description T7 SDICLK I SDRAM Clock In: SDRAM clock input for the SDRAM memory controller interface. U7 SDOCLK O System/SDRAM Clock Out: Output of the internal system clock, it is also used as the clock signal for SDRAM interface. P4 ADDR21/BA1 O Address Bit 21/Bank Address Input 1: Address bit 21 for asynchronous accesses. Bank Address Input bit 1 for SDRAM accesses. P3 ADDR20/BA0 O Address Bit 20/Bank Address Input 0: Address bit 20 for asynchronous accesses. Bank Address Input bit 0 for SDRAM accesses. M3 M2 M1 N4 N3 N2 N1 P2 P1 R3 R2 R1 T2 T1 U1 U2 T3 U3 T4 U4 ADDR[19] ADDR[18] ADDR[17] ADDR[16] ADDR[15] ADDR[14] ADDR[13] ADDR[12] ADDR[11] ADDR[10] ADDR[9] ADDR[8] ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0] O Address Bus: The 22-bit address bus (including ADDR[21:20] above) covers 4M word memory space shared by ROM/SRAM/FLASH, SDRAM, and external I/O banks. During the SDRAM cycles, the internal address bus is used to generate RAS and CAS addresses for the SDRAM. The number of column address bits in the SDRAM banks can be programmed from 8 to 11 bits via the SDRAM control registers. ADDR[12:0] are the SDRAM address and ADDR[21:20] are the SDRAM bank address. During other cycles, the ADDR[21:0] is the byte address of the data transfer. For SDRAM and FLASH/ROM/SRAM, connect all address lines, i.e. A0 to A0, A1 to A1, etc. The memory controller automatically handles address line adjustments for the 8/16/32 bit accesses. For external I/O devices, the user needs to connect address lines for 8/16/32 bit accesses. Note : 1. I = Input. O = Output. I/O = Bidirectional. |
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