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SC4524C Datasheet(PDF) 15 Page - Semtech Corporation |
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SC4524C Datasheet(HTML) 15 Page - Semtech Corporation |
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15 / 21 page  SC4524C 15 switching time of the NPN transistor (see Table 4). Table 4. Typical switching time In addition, the quiescent current loss is (11) The total power loss of the SC4524C is therefore (12) The temperature rise of the SC4524C is the product of the total power dissipation (Equation (12)) and q JA (36 o C/W), which is the thermal impedance from junction to ambient for the SOIC-8 EDP package. It is not recommended to operate the SC4524C above 125oC junction temperature. In the applications with high input voltage and high output current, the switching frequency may need to be reduced to meet the thermal requirement. O CESAT C I V D P ⋅ ⋅ = 40 I V D P O BST BST ⋅ ⋅ = DC 2 O IND R I ) 3 . 1 ~ 1 . 1 ( P ⋅ ⋅ = O D D I V ) D 1 ( P ⋅ ⋅ − = SW O IN S SW F I V t 2 1 P ⋅ ⋅ ⋅ ⋅ = Q BST SW C TOTAL P P P P P + + + = mA 2 V P IN Q ⋅ = O CESAT C I V D P ⋅ ⋅ = 40 I V D P O BST BST ⋅ ⋅ = DC 2 O IND R I ) 3 . 1 ~ 1 . 1 ( P ⋅ ⋅ = O D D I V ) D 1 ( P ⋅ ⋅ − = SW O IN S SW F I V t 2 1 P ⋅ ⋅ ⋅ ⋅ = Q BST SW C TOTAL P P P P P + + + = mA 2 V P IN Q ⋅ = O CESAT C I V D P ⋅ ⋅ = 40 I V D P O BST BST ⋅ ⋅ = DC 2 O IND R I ) 3 . 1 ~ 1 . 1 ( P ⋅ ⋅ = O D D I V ) D 1 ( P ⋅ ⋅ − = SW O IN S SW F I V t 2 1 P ⋅ ⋅ ⋅ ⋅ = Q BST SW C TOTAL P P P P P + + + = mA 2 V P IN Q ⋅ = O CESAT C I V D P ⋅ ⋅ = 40 I V D P O BST BST ⋅ ⋅ = DC 2 O IND R I ) 3 . 1 ~ 1 . 1 ( P ⋅ ⋅ = O D D I V ) D 1 ( P ⋅ ⋅ − = SW O IN S SW F I V t 2 1 P ⋅ ⋅ ⋅ ⋅ = Q BST SW C TOTAL P P P P P + + + = mA 2 V P IN Q ⋅ = PCB Layout Considerations In a step-down switching regulator, the input bypass capacitor, the main power switch and the freewheeling diode carry pulse current (Figure 9). For jitter-free operation,thesizeoftheloopformedbythesecomponents should be minimized. Since the power switch is already integrated within the SC4524C, connecting the anode of the freewheeling diode close to the negative terminal of the input bypass capacitor minimizes size of the switched current loop. The input bypass capacitor should be placed close to the IN pin. Shortening the traces of the SW and BST nodes reduces the parasitic trace inductance at these nodes. This not only reduces EMI but also decreases switching voltage spikes at these nodes. The exposed pad should be soldered to a large ground plane as the ground copper acts as a heat sink for the device. To ensure proper adhesion to the ground plane, avoid using vias directly under the device. Figure 9. Heavy lines indicate the critical pulse current loop. The stray inductance of this loop should be minimized. 12 12 Fig.9 Vout Vin + + Currents in Power Section IN V OUT V L Z 12 12 Fig.9 Vout Vin + + Currents in Power Section IN V OUT V L Z 1A 2A 12V 12.5ns 15.3ns 24V 22ns 25ns 28V 25.3ns 28ns Load Current Input Voltage |
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Similar Description - SC4524C |
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