TSOP40 Standard

TSOP40 Reversed

Pin Functions

Function Logic

Command Settings

No. 5239-3/14

LE28F4001M, T, R-15/20

Symbol

Pin

Functions

A18 to A0

Address input

Supply the memory address to these pins.

The address is latched internally during a write cycle.

These pins output data during a read cycle and input data during a write cycle.

DQ7 to DQ0

Data input and output

Data is latched internally during a write cycle.

Outputs go to the high-impedance state when either OE or CE is high.

CE

Chip enable

The device is active when CE is low.

When CE is high, the device becomes unselected and goes to the standby state.

OE

Output enable

Makes the data output buffers active.

OE is a low-active input.

WE

Write enable

Makes the write operation active.

WE is a low-active input.

Power supply

Apply 5 V (±10%) to this pin.

Ground

N.C.

No connection

These pins must be left open.

Mode

CE

OE

WE

A18 to A0

DQ7 to DQ0

Read

Write

Standby or write inhibit

X

X

X

High-Z

Write inhibit

X

X

X

X

X

X

Manufacturer code (BF)

Product identification

Device code (04)

Command

Request

Setup command cycle

Execute command cycle

SDP

cycle

Operation

Address

Data

Operation

Address

Data

Sector erase

2

Write

X

20H

Write

SA

D0H

N

Byte program

2

Write

X

10H

Write

PA

PD

N

Reset

1

Write

X

FFH

Y

Read ID

3

Write

X

90H

Read

(7)

(7)

Y

Software data unprotect

7

See Figure 9.

Software data protect

7

See Figure 10.